SLVUBE6C November 2018 – July 2021 TPS56339
5.9 Powering Down
Figure 5-12 and Figure 5-13 show the start-up waveforms for the TPS56339EVM. In Figure 5-12, the output voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the R1 and R2 resistor divider network. In Figure 5-13, the output is inhibited by using a 5-V logic signal between EN and GND. The input voltage for these plots is 19 V and the load current is 3 A.
Figure 5-12 TPS56339EVM Shutdown Relative to VIN
Figure 5-13 TPS56339EVM Shutdown Relative to EN