SLVUBW7 May   2020

 

  1.   TPS7H4001QEVM-CVAL Evaluation Module User's Guide
    1.     Trademarks
    2. 1 TPS7H4001QEVM-CVAL Overview
      1. 1.1 Features
      2. 1.2 Applications
    3. 2 TPS7H4001QEVM-CVAL Default Configuration
    4. 3 TPS7H4001QEVM-CVAL Initial Setup
    5. 4 TPS7H4001QEVM-CVAL Testing
      1. 4.1 Output Voltage Regulation
      2. 4.2 Quadrature Phases
      3. 4.3 Output Voltage Ripple
      4. 4.4 Soft Startup
      5. 4.5 Transient Response to Positive/Negative Load Step (27 A to 67 A to 27 A)
      6. 4.6 Loop Frequency Response
      7. 4.7 Efficiency
      8. 4.8 Current Limiting
      9. 4.9 Current Sharing
    6. 5 TPS7H4001QEVM-CVAL EVM Schematic
    7. 6 TPS7H4001QEVM-CVAL Bill of Materials (BOM)
    8. 7 Board Layout
    9. 8 Appendix A

2 TPS7H4001QEVM-CVAL Default Configuration

Table 1 describes the default configuration of the TPS7H4001QEVM-CVAL listing the external components that define the complete parallel converter design.

Table 1. Default EVM Configuration

PARAMETER SPECIFICATIONS DESCRIPTION
Input power supply 5 V Bound by UVLO enable circuit (R5, R6)
Regulated output voltage 1 V R19 (RTOP) = 10 kΩ, R26 (RBOTTOM) = 15.4 kΩ
LOUT per converter 0.9 µH Chosen to meet inductor ripple current of 10% (Kind = 0.1)
COUT per converter 1980 µF Chosen for (1) ESR = 1 mΩ to set output voltage ripple; (2) value used during single event effects testing ensuring regulation maintained with single event upset to switching
Output current per converter 0 to 18 A By design
Switching frequency 500 kHz Set by R9 (RT) = 174 kΩ
Soft start time constant ≈2 ms Set by C13 (Css) = 39 nF
UVLO enable rising ≈4.249 V Set by R5 = 10 kΩ and R6 = 3.4 kΩ
UVLO enable falling ≈4.011 V Set by R5 = 10 kΩ and R6 = 3.4 kΩ
Loop bandwidth ≈25 kHz Set by operational transconductance amplifier (OTA) compensation circuit: R7 (RCOMP) = 2 kΩ, C15 (CCOMP) = 33 nF, C14 (CHF) = 330 pF
Loop phase margin ≈60°
Gain margin ≈–25 dB