SLVUCG9 October   2022 TPS36-Q1

 

  1.   Abstract
  2. 1Trademarks
  3. 2Introduction
    1. 2.1 Related Documentation
  4. 3Schematic, Bill of Materials, and Layout
    1. 3.1 TPS36Q1EVM Schematic
    2. 3.2 TPS36Q1EVM Bill of Materials
    3. 3.3 Layout and Component Placement
  5. 4EVM Connectors
    1. 4.1 EVM Jumpers
    2. 4.2 EVM Test Points
  6. 5EVM Setup and Operation
    1. 5.1 Input Power (VDD)
    2. 5.2 RESET
    3. 5.3 Manual Reset (MR)
    4. 5.4 SET0 and SET1
    5. 5.5 Watchdog Enable (WD_EN)
    6. 5.6 Watchdog Input (WDI)
    7. 5.7 Watchdog Output (WDO)
    8. 5.8 CRST
    9. 5.9 CWD
  7. 6EVM Performance Results
  8. 7Revision History

EVM Test Points

Test points are placed throughout the board and are used to verify pin functionality. Each device configuration option letter has different pinouts, so each test point can serve different purposes depending on the chosen IC. For example, test point 1 (TP1) is used to monitor pin 1, but the functionality of pin 1 varies between MR, SET0, and CWD as seen in Figure 4-1. Jumpers can be used with shunt jumpers to connect two pins together in order to serve multiple testing purposes. For example, connecting pins 7-8 of jumper J1 connects pin 1 to VDD, a logic high, and connecting pins 5-6 of jumper J1 connects pin 1 to GND, a logic low. Pins can also be connected to delay capacitors via the jumpers, and these connections can be used to adjust programmable timeout periods.

GUID-78EA339D-50FB-44D4-9623-6F0A9489B6B2-low.pngFigure 4-1 Schematic Closeup