SLVUD02 April   2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Alternate Board Configurations
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Important Usage Notes
    3. 2.3 Connector Descriptions
  7. 3Implementation Results
    1. 3.1 Default Configuration Results
    2. 3.2 Enable and Disable
    3. 3.3 Undervoltage and Overvoltage Monitoring (MODE=0)
    4. 3.4 Window and Overvoltage Monitoring (MODE=1)
    5. 3.5 WDOb
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
    1. 5.1 Compliance and Certifications
  10. 6Related Documentation

1.3 Specification

TPS7H3024EVM-CVAL Default Configuration Simplified SchematicFigure 1-1 Default Configuration Simplified Schematic.
Table 1-1 Default EVM Configuration

Specification

Value

Description

Input Voltage

VIN

12V

Falls within the recommended device input voltage range of 3V to 14V.

Turn On Threshold

10.3V

VIN rising/falling value that turns the device ON/OFF.

Set by:

R20 = 10 kΩ

R21 = 620 Ω

Turn Off Threshold

8.6V

PULL_UP1 Voltage

1.8V

Voltage used by all RESETb outputs. Falls within the recommended device input voltage range of 1.6V to 7V.

PULL_UP2 Voltage

1.8V

Voltage used by WDOb and PWRGD outputs. Falls within the recommended device input voltage range of 1.6V to 7V.

VOUT1 VRISE Threshold

2.22V

(89 % of 2.5V)

Rising and falling voltage thresholds where the monitored VOUT rail is considered IN or OUT of regulation, respectively.

Set by:

R22 = 5.17 kΩ

R25 = 1.91 kΩ

VOUT1 VFALL Threshold

2.10V

(84 % of 2.5V)

VOUT2 VRISE Threshold

3.46 V

(105 % of 3.3V)

Rising and falling voltage thresholds where the monitored VOUT rail is considered IN or OUT of regulation, respectively.

Set by:

R23 = 5.49 kΩ

R26 = 1.15 kΩ

VOUT2 VFALL Threshold

3.33 V

(101 % of 3.3V)

VOUT3 VRISE Threshold

0.79 V

(99 % of 0.8V)

Rising and falling voltage thresholds where the monitored VOUT rail is considered IN or OUT of regulation, respectively.

Set by:

R28 = 1.33 kΩ

R31 = 4.12 kΩ

VOUT3 VFALL Threshold

0.76 V

(95 % of 0.8V)

VOUT4 VRISE Threshold

1.99 V

(111 % of 1.8V)

Rising and falling voltage thresholds where the monitored VOUT rail is considered IN or OUT of regulation, respectively.

Set by:

R29 = 3.74 kΩ

R32 = 1.62 kΩ

VOUT4 VFALL Threshold

1.90 V

(106 % of 1.8V)

RESETb Delay Time

tDLY_TMR

12.5 ms

Programmable time delay between when the condition for a RESETb signal to go HIGH is met and when the signal actually transitions.

Set by:

R15 = 619 kΩ

J14 shunted

Watchdog Timer

tWD_TMR

1 s

Programmable timer that sets the amount of time allowed netween rising edges sensed at the WDI pin in order for WDOb to remain HIGH. If the timer expires, the WDOb output will go low until the next sensed rising edge at WDI.

Set by:

R18 = 118 kΩ

J17 shunted