SLVUD02A April   2025  – May 2026

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Negative Rail Sensing
      2. 1.3.2 Configuration for Push-Pull vs Open-Drain
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Important Usage Notes
    3. 2.3 Connector Descriptions
  7. 3Implementation Results
    1. 3.1 Default Configuration Results
    2. 3.2 Enable and Disable
    3. 3.3 Undervoltage and Overvoltage Monitoring (MODE=0)
    4. 3.4 Window and Overvoltage Monitoring (MODE=1)
    5. 3.5 WDOb
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials (BOM)
    3. 4.3 PCB Layouts
  9. 5Compliance Information
    1. 5.1 Compliance and Certifications
  10. 6Related Documentation
  11. 7Revision History

3.4 Window and Overvoltage Monitoring (MODE=1)

For the following tests, J32 is shunted to hold the MODE pin HIGH to select 2x Window + 2x Overvoltage monitoring mode. Voltages are kept in regulation for the pair of channels not shown in the scope capture.

TPS7H3xx4EVM-CVAL Channel 1/2 Regulation Monitoring with DLY_TMR Floating Figure 3-8 Channel 1/2 Regulation Monitoring with DLY_TMR Floating
TPS7H3xx4EVM-CVAL Channel 3/4 Regulation Monitoring with DLY_TMR Floating Figure 3-9 Channel 3/4 Regulation Monitoring with DLY_TMR Floating