SLVUD11 March   2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Transient Load Circuit
    2. 2.2 Connector Descriptions
    3. 2.3 Best Practices
  7. 3Implementation Results
    1. 3.1 Evaluation Setup
    2. 3.2 Switch Nodes
    3. 3.3 Output Voltage Ripple
    4. 3.4 Soft Start
    5. 3.5 Load Steps
    6. 3.6 Bode Plot
    7. 3.7 Efficiency Results
    8. 3.8 Current Sharing
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
    1. 5.1 Compliance and Certifications
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7Related Documentation
    1. 7.1 Supplemental Content

PCB Layouts

TPS7H4011QEVM-CVAL Top Overlay Figure 4-5 Top Overlay
TPS7H4011QEVM-CVAL Solder Mask (Top View) Figure 4-6 Solder Mask (Top View)
TPS7H4011QEVM-CVAL Layer 1 (Top View) Figure 4-7 Layer 1 (Top View)
TPS7H4011QEVM-CVAL Layer 2 Figure 4-8 Layer 2
TPS7H4011QEVM-CVAL Layer 3 Figure 4-9 Layer 3
TPS7H4011QEVM-CVAL Layer 4 Figure 4-10 Layer 4
TPS7H4011QEVM-CVAL Layer 5 Figure 4-11 Layer 5
TPS7H4011QEVM-CVAL Layer 6 Figure 4-12 Layer 6
TPS7H4011QEVM-CVAL Layer 7 Figure 4-13 Layer 7
TPS7H4011QEVM-CVAL Layer 8 (Bottom View) Figure 4-14 Layer 8 (Bottom View)
TPS7H4011QEVM-CVAL Solder Mask (Bottom
                    View) Figure 4-15 Solder Mask (Bottom View)
TPS7H4011QEVM-CVAL Drill Drawing Figure 4-16 Drill Drawing