SLVUDY9 September   2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Jumper Information
    3. 2.3 Setup
  8. 3Software
    1. 3.1 GUI Installation
    2. 3.2 Software Description
      1. 3.2.1 DAC90802 Register Page
      2. 3.2.2 DAC90802 DC Output Page
      3. 3.2.3 DC Linearity Page
      4. 3.2.4 Arbitrary Waveform Generation Page
        1. 3.2.4.1 Quick Start
        2. 3.2.4.2 GUI Control Reference
        3. 3.2.4.3 Update Rate
      5. 3.2.5 Multiplying Mode Page
        1. 3.2.5.1 Multiplying Bandwidth Measurement Setup
        2. 3.2.5.2 Multiplying THD Measurement
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  10. 5Compliance Information
    1. 5.1 Compliance and Certifications
  11. 6Related Documentation

3.2.4.3 Update Rate

The DAC update rate determines the waveform sampling rate and depends on the selected SCLK frequency and SPI. Table 3-3 shows the SPI, maximum update rate and device mode of operation supported by DAC90802EVM GUI. QSPI DDR STREAM is optimized to demonstrate device maximum update rate as per the design specification. Other SPI can be further optimized to get better update rate. For more information see the datasheet of the DAC90802EVM.

Table 3-3 DAC90802EVM GUI Control Reference
SPI MAXIMUM UPDATE RATE DEVICE MODE OF OPERATION
CSPI SDR SCLK/37 High precision
CSPI DDR SCLK/21 High precision
DSPI SDR SCLK/21 High precision
DSPI DDR SCLK/13 High precision
QSPI SDR SCLK/13 High precision
QSPI DDR SCLK/9 High precision
QSPI DDR STREAM SCLK/3 High precision
QSPI DDR STREAM SCLK/2 High speed

Example: For an SCLK frequency of 66MHz:

  • High speed mode → 33MHz DAC update rate.
  • High precision + QSPI DDR → 7.333MHz DAC update rate.
  • High precision + QSPI DDR STREAM → 22MHz DAC update rate.