Defining noise and precision in a power architecture

Power-supply noise is random and occurs in all semiconductor power devices and power topologies. The focus of this white paper is signals below 100 kHz, as signals above this are often attributable to switching ripple or electromagnetic interference (EMI). You can also further separate noise into low-frequency noise (0.1 Hz to 10 Hz) and high-frequency noise (100 Hz to 100 kHz), with differing requirements and design challenges, as shown in Figure 4.

Low-frequency noise is often specified as the peak-to-peak noise between 0.1 Hz and 10 Hz that a semiconductor device naturally produces given the combination of its silicon properties and design architecture. This low-frequency noise is often visible in an oscilloscope when zooming into a voltage rail at high resolution, as shown in Figure 5, and is often the cause of errors in precision DC measurements. ADC applications where low-frequency noise is a critical specification include battery measurements, energy metering, seismic measurements and even semiconductor test measurements.

The alternative is high-frequency noise, which is in the band of 100 Hz to 100 kHz and can include white noise, switching noise and clock jitter, as shown in Figure 6. High-frequency noise sources can also come from the environment, through coupling from EMI. For example, an ADC can experience errors from a noisy power supply. EMI from the same noisy power supply can lead to increased clock jitter, which if excessive can degrade signal-to-noise performance.

It is becoming increasingly important to lower high-frequency noise caused by rising clock frequencies in digital circuits, which are more susceptible to jitter. ADC applications where high-frequency noise is a critical specification include power-line quality monitors, digital signal processing applications and radio-frequency (RF) communications equipment.