SNAA396A February   2024  – January 2025 LMK5B33216 , LMK5B33414

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1800G Market Trend
  5. 2LMK5B33216 for 112G and 224G PAM4 SerDes Applications
  6. 3LMK5B33216 Overview
  7. 4LMK5B33216 Performance
    1. 4.1 RMS Jitter
    2. 4.2 BAW Technology
    3. 4.3 Phase Noise Profile
  8. 5LMK5B33216 Features
    1. 5.1 Frequency and Phase Adjustments
    2. 5.2 Input Reference Switching
    3. 5.3 Holdover
    4. 5.4 Zero-Delay Mode
  9. 6Summary
  10. 7References
  11. 8Revision History

4.1 RMS Jitter

Table 4-2 demonstrates additional RMS jitter data across various integration ranges.

Table 4-2 Jitter Performance of the LMK5B33216 Across Different Integration Ranges
Output Clock Frequency [MHz] RMS Jitter (typ.) [fs](1) Jitter Integration Range [MHz]
156.25(2) 47 0.012 to 20
26 0.100 to 5
31 0.750 to 10
71 0.200 to 50
15 2 to 4
39 4 to 20
312.5(3) 42 0.012 to 20
19 0.100 to 5
21 0.750 to 10
47 0.200 to 50
10 2 to 4
26 4 to 20
625(4) 35 0.012 to 20
12 0.100 to 5
11 0.750 to 10
25 0.200 to 50
5 2 to 4
13 4 to 20
(1) The measurements were taken using an XO input frequency of 48MHz with all LMK5B33216 outputs set to the same frequency with an output swing (VOD) ≥ 800mV.
(2) The APLL3 post divider is 16.
(3) The APLL3 post divider is 8.
(4) The APLL3 post divider is 4.