SNAA396A February   2024  – January 2025 LMK5B33216 , LMK5B33414

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1800G Market Trend
  5. 2LMK5B33216 for 112G and 224G PAM4 SerDes Applications
  6. 3LMK5B33216 Overview
  7. 4LMK5B33216 Performance
    1. 4.1 RMS Jitter
    2. 4.2 BAW Technology
    3. 4.3 Phase Noise Profile
  8. 5LMK5B33216 Features
    1. 5.1 Frequency and Phase Adjustments
    2. 5.2 Input Reference Switching
    3. 5.3 Holdover
    4. 5.4 Zero-Delay Mode
  9. 6Summary
  10. 7References
  11. 8Revision History

8 Revision History

Changes from Revision * (February 2024) to Revision A (January 2025)

  • Added data center clocking design block diagramGo
  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added 224G PAM4 SerDes description throughout the documentGo
  • Changed from PAM-4 to PAM4Go
  • Updated by combining Introduction into the 800G Market Trend sectionGo
  • Changed LMK5B33216 for Ethernet Applications title to LMK5B33216 for 112G and 224G PAM4 SerDes Applications Go
  • Added LMKDB1108 descriptionGo
  • Updated the full system design block diagramGo
  • Changed LMK5B33216 for SerDes Applications title to LMK5B33216 Overview and rearranged textGo
  • Changed LMK5B33216 for SerDes Applications title to LMK5B33216 Performance and rearranged textGo
  • Changed figure title from General Phase Noise Plot to General Phase Noise Plot of a Network Synchronizer Output Clock Go