SNAA396A February   2024  – January 2025 LMK5B33216 , LMK5B33414

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1800G Market Trend
  5. 2LMK5B33216 for 112G and 224G PAM4 SerDes Applications
  6. 3LMK5B33216 Overview
  7. 4LMK5B33216 Performance
    1. 4.1 RMS Jitter
    2. 4.2 BAW Technology
    3. 4.3 Phase Noise Profile
  8. 5LMK5B33216 Features
    1. 5.1 Frequency and Phase Adjustments
    2. 5.2 Input Reference Switching
    3. 5.3 Holdover
    4. 5.4 Zero-Delay Mode
  9. 6Summary
  10. 7References
  11. 8Revision History

2 LMK5B33216 for 112G and 224G PAM4 SerDes Applications

The LMK5B33216 is used to jitter-clean SyncE or PHY recovered clocks and provide synchronized, low-jitter, outputs to the ASIC and CPU.

Figure 2-1 shows the full system design for an 800G switch using the LMK5B33216. Pairing the LMK6Cx (TI’s BAW-based LVCMOS oscillator family) with the LMK5B33216 yields a low-cost option for the XO input. Additional clocks can be fanned out to the ASIC through a 4, 8, 12, or 16 output, low additive jitter, and clock buffer from the LMK1Dxxxx family, such as the LMK1D1204.

The LMK3H0102 is a reference-less, BAW-based, clock generator used to clock up to two PCIe Gen 1 to PCIe Gen 6 compliant outputs. Each LMK3H0102 output is capable of generating any frequency between 2.5MHz and 400MHz by dividing down from two fractional output dividers (FODs).

Full System Design for 800G Switch ApplicationsFigure 2-1 Full System Design for 800G Switch Applications