SNAS491C February   2010  – January 2025 LM48580

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: VDD = 3.6 V #GUID-238D0643-98EF-4676-B2E1-A584A5DF74F7/SNAS491599
    6. 5.6 Typical Performance Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Class H Operation
      2. 6.3.2 Properties of Piezoelectric Elements
      3. 6.3.3 Differential Amplifier Explanation
      4. 6.3.4 Thermal Shutdown
      5. 6.3.5 Gain Setting
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Function
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Proper Selection of External Components
          1. 7.2.1.1.1 Boost Converter Capacitor Selection
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Boost Converter Output Capacitor Selection
          1. 7.2.2.1.1 Inductor Selection
          2. 7.2.2.1.2 Diode Selection
        2. 7.2.2.2 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Community Resources
    4. 8.4 Trademarks
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

7.3 Power Supply Recommendations

The LM48580 device is designed be operate with a power supply between 2.5 V and 5.5 V. Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 1-μF ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required