SNAS801D June   2020  – May 2026 LMK05318B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: 4-Layer JEDEC Standard PCB
    5. 6.5 Thermal Information: 10-Layer Custom PCB
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Output Clock Test Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 8.2 Functional Block Diagram
      1. 8.2.1 PLL Architecture Overview
      2. 8.2.2 DPLL Mode
      3. 8.2.3 APLL-Only Mode
    3. 8.3 Feature Description
      1. 8.3.1  Oscillator Input (XO_P/N)
      2. 8.3.2  Reference Inputs (PRIREF_P/N and SECREF_P/N)
        1. 8.3.2.1 Programmable Input Hysteresis
      3. 8.3.3  Clock Input Interfacing and Termination
      4. 8.3.4  Reference Input Mux Selection
        1. 8.3.4.1 Automatic Input Selection
        2. 8.3.4.2 Manual Input Selection
      5. 8.3.5  Hitless Switching
      6. 8.3.6  Gapped Clock Support on Reference Inputs
      7. 8.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 8.3.7.1 XO Input Monitoring
        2. 8.3.7.2 Reference Input Monitoring
          1. 8.3.7.2.1 Reference Validation Timer
          2. 8.3.7.2.2 Amplitude Monitor
          3. 8.3.7.2.3 Frequency Monitoring
          4. 8.3.7.2.4 Missing Pulse Monitor (Late Detect)
          5. 8.3.7.2.5 Runt Pulse Monitor (Early Detect)
          6. 8.3.7.2.6 1PPS Phase Validation Monitor
            1. 8.3.7.2.6.1 Check XO Input Frequency Accuracy for 1PPS Lock
        3. 8.3.7.3 PLL Lock Detectors
        4. 8.3.7.4 Tuning Word History
        5. 8.3.7.5 Status Outputs
        6. 8.3.7.6 Interrupt
      8. 8.3.8  PLL Relationships
        1. 8.3.8.1  PLL Frequency Relationships
        2. 8.3.8.2  Analog PLLs (APLL1, APLL2)
        3. 8.3.8.3  APLL Reference Paths
          1. 8.3.8.3.1 APLL XO Doubler
          2. 8.3.8.3.2 APLL1 XO Reference (R) Divider
          3. 8.3.8.3.3 APLL2 Reference (R) Dividers
        4. 8.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 8.3.8.5  APLL Feedback Divider Paths
          1. 8.3.8.5.1 APLL1N Divider With SDM
          2. 8.3.8.5.2 APLL2N Divider With SDM
        6. 8.3.8.6  APLL Loop Filters (LF1, LF2)
        7. 8.3.8.7  APLL Voltage Controlled Oscillators (VCO1, VCO2)
          1. 8.3.8.7.1 VCO Calibration
        8. 8.3.8.8  APLL VCO Clock Distribution Paths (P1, P2)
        9. 8.3.8.9  DPLL Reference (R) Divider Paths
        10. 8.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 8.3.8.11 DPLL Loop Filter (DLF)
        12. 8.3.8.12 DPLL Feedback (FB) Divider Path
      9. 8.3.9  Output Clock Distribution
      10. 8.3.10 Output Channel Muxes
      11. 8.3.11 Output Dividers (OD)
      12. 8.3.12 Clock Outputs (OUTx_P/N)
        1. 8.3.12.1 AC-Differential Output (AC-DIFF)
        2. 8.3.12.2 HCSL Output
        3. 8.3.12.3 1.8V LVCMOS Output
        4. 8.3.12.4 Output Auto-Mute During LOL
      13. 8.3.13 Glitchless Output Clock Start-Up
      14. 8.3.14 Clock Output Interfacing and Termination
      15. 8.3.15 Output Synchronization (SYNC)
      16. 8.3.16 1PPS Input to Output Phase Alignment (PRIREF-to-OUT7 SYNC)
        1. 8.3.16.1 PRIREF-to-OUT7 SYNC Phase Calculation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Start-Up
        1. 8.4.1.1 Device Power-On Reset (POR)
        2. 8.4.1.2 PLL Start-Up Sequence
        3. 8.4.1.3 HW_SW_CTRL Pin Functionalities
        4. 8.4.1.4 Using the EEPROM
      2. 8.4.2 PLL Operating Modes
        1. 8.4.2.1 Free-Run Mode
        2. 8.4.2.2 Lock Acquisition
        3. 8.4.2.3 Locked Mode
        4. 8.4.2.4 Holdover Mode
      3. 8.4.3 Digitally-Controlled Oscillator (DCO) Mode
        1. 8.4.3.1 DCO Frequency Step Size
        2. 8.4.3.2 DCO Direct-Write Mode
    5. 8.5 Programming
      1. 8.5.1 Interface and Control
      2. 8.5.2 I2C Serial Communication
        1. 8.5.2.1 I2C Block Register Transfers
      3. 8.5.3 SPI Serial Communication
        1. 8.5.3.1 SPI Block Register Transfer
      4. 8.5.4 Register Map and EEPROM Map Generation
      5. 8.5.5 General Register Programming Sequence
      6. 8.5.6 EEPROM Programming Flow
        1. 8.5.6.1 EEPROM Programming Using Method #1 (Register Commit)
          1. 8.5.6.1.1 Write SRAM Using Register Commit
          2. 8.5.6.1.2 Program EEPROM
        2. 8.5.6.2 EEPROM Programming Using Method #2 (Direct Writes)
          1. 8.5.6.2.1 Write SRAM Using Direct Writes
          2. 8.5.6.2.2 User-Programmable Fields In EEPROM
      7. 8.5.7 Read SRAM
      8. 8.5.8 Read EEPROM
      9. 8.5.9 EEPROM Start-up Mode Default Configuration
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Start-Up Sequence
      2. 9.1.2 Power Down (PDN) Pin
      3. 9.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 9.1.3.1 Mixing Supplies
        2. 9.1.3.2 Power-On Reset (POR) Circuit
        3. 9.1.3.3 Powering Up From a Single-Supply Rail
        4. 9.1.3.4 Power Up From Split-Supply Rails
        5. 9.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 9.1.4 Slow or Delayed XO Start-Up
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Supply Bypassing
      2. 9.4.2 Device Current and Power Consumption
        1. 9.4.2.1 Current Consumption Calculations
        2. 9.4.2.2 Power Consumption Calculations
        3. 9.4.2.3 Example
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Reliability
        1. 9.5.3.1 Support for PCB Temperature up to 105°C
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TICS Pro
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

11 Revision History

Changes from December 10, 2025 to May 4, 2026 (from Revision C (December 2025) to Revision D (May 2026))

  • Updated the Pin Functions and Configurations to reflect changes to the recommended VDD bypass capacitor value from 0.1μF to 10μFGo

Changes from Revision B (June 2021) to Revision C (December 2025)

  • Changed the title of the data sheetGo
  • Changed all instances of legacy terminology for SPI (to controller and peripheral) and I2C (to controller and target)Go
  • Removed mention of ROM throughout the documentGo
  • Corrected output format type from LVPECL to AC-LVPECL throughout the documentGo
  • Updated the Features sectionGo
  • Added hyperlinks to the Applications sectionGo
  • Clarified the Description sectionGo
  • Added the Device Comparison sectionGo
  • Clarified Output and VDDO pin descriptionsGo
  • Changed the recommended VDD bypass capacitor value from 0.1μF to 10μFGo
  • Changed the XO Input Buffer Modes section to remove leading zeroesGo
  • Changed the Reference Input Buffer Modes section to remove leading zeroesGo
  • Corrected "Single-Ended LVCMOS to Reference" termination diagramGo
  • Changed the tables in the Manual Input Selection sectionGo
  • Added descriptions for reference frequency monitoringGo
  • Changed Zero-Delay Mode (ZDM) Synchronization for 1PPS Input and Output title to 1PPS Input to Output Phase Alignment (PRIREF-to-OUT7 SYNC) and clarified featureGo
  • Added the Device Power-On Reset (POR) sectionGo
  • Renamed Device Start-Up Mode from the Pin Configuration and Functions section to HW_SW_CTRL Pin Functionalities and moved section to Detailed Description Go
  • Clarified ROM boot-up in the HW_SW_CTRL Pin Functionalities sectionGo
  • Removed custom EEPROM inquiryGo
  • Renamed the EEPROM Mode section to Using the EEPROM Go
  • Clarified the Using the EEPROM sectionGo
  • Clarified the 5 MSBs of I2C (11001b) can be programmed in EEPROM Go
  • Corrected number of I2C addresses through GPIO1 from 4 to 3 Go
  • Clarified EEPROM programming stepsGo
  • Clarified registers requiring SRAM direct write methodGo
  • Changed SLAVEADR to I2C_ADDRGo

Changes from Revision A (January 2021) to Revision B (June 2021)

  • Changed data sheet title from: LMK05318B Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains to: LMK05318B Ultra-Low Jitter Clock Generator Go
  • Added systems block diagramGo
  • Added Vod for specific fOUT test conditions for AC-LVDS, AC-CML, and AC-LVPECLGo
  • Changed VIL max from 0.5 to 0.6 on SCL/SDA pinGo
  • Changed SLAVEADR byte number from: 5 to: 10Go
  • Clarified reading NVM Spare BytesGo

Changes from Revision * (June 2020) to Revision A (January 2021)

  • Changed the typical RMS jitter at 155.52MHz from 130fs to 125fs Go
  • Changed the maximum APLL1 PFD frequency from 50 MHz to 80 MHzGo
  • Changed the maximum AC-LVDS output frequency from 800 MHz to 1250 MHzGo
  • Changed the maximum AC-CML output frequency from 800 MHz to 1250 MHzGo
  • Changed the maximum AC-LVPECL output frequency from 800 MHz to 1250 MHzGo
  • Changed the output format in RMS jitter test conditions from AC-DIFF to AC-LVPECLGo
  • Changed the max RMS jitter for 312.5 MHz from 100 fs to 80 fsGo
  • Changed the max RMS jitter for 156.25 MHz from 100 fs to 90 fsGo
  • Changed the max RMS jitter for 153.6 MHz from 250 fs to 200 fsGo
  • Changed the max RMS jitter for 155.52 MHz from 250 fs to 200 fsGo
  • Added typical performance plot for output voltage swing vs. output frequencyGo