SNAS801D June   2020  – May 2026 LMK05318B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: 4-Layer JEDEC Standard PCB
    5. 6.5 Thermal Information: 10-Layer Custom PCB
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Output Clock Test Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 8.2 Functional Block Diagram
      1. 8.2.1 PLL Architecture Overview
      2. 8.2.2 DPLL Mode
      3. 8.2.3 APLL-Only Mode
    3. 8.3 Feature Description
      1. 8.3.1  Oscillator Input (XO_P/N)
      2. 8.3.2  Reference Inputs (PRIREF_P/N and SECREF_P/N)
        1. 8.3.2.1 Programmable Input Hysteresis
      3. 8.3.3  Clock Input Interfacing and Termination
      4. 8.3.4  Reference Input Mux Selection
        1. 8.3.4.1 Automatic Input Selection
        2. 8.3.4.2 Manual Input Selection
      5. 8.3.5  Hitless Switching
      6. 8.3.6  Gapped Clock Support on Reference Inputs
      7. 8.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 8.3.7.1 XO Input Monitoring
        2. 8.3.7.2 Reference Input Monitoring
          1. 8.3.7.2.1 Reference Validation Timer
          2. 8.3.7.2.2 Amplitude Monitor
          3. 8.3.7.2.3 Frequency Monitoring
          4. 8.3.7.2.4 Missing Pulse Monitor (Late Detect)
          5. 8.3.7.2.5 Runt Pulse Monitor (Early Detect)
          6. 8.3.7.2.6 1PPS Phase Validation Monitor
            1. 8.3.7.2.6.1 Check XO Input Frequency Accuracy for 1PPS Lock
        3. 8.3.7.3 PLL Lock Detectors
        4. 8.3.7.4 Tuning Word History
        5. 8.3.7.5 Status Outputs
        6. 8.3.7.6 Interrupt
      8. 8.3.8  PLL Relationships
        1. 8.3.8.1  PLL Frequency Relationships
        2. 8.3.8.2  Analog PLLs (APLL1, APLL2)
        3. 8.3.8.3  APLL Reference Paths
          1. 8.3.8.3.1 APLL XO Doubler
          2. 8.3.8.3.2 APLL1 XO Reference (R) Divider
          3. 8.3.8.3.3 APLL2 Reference (R) Dividers
        4. 8.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 8.3.8.5  APLL Feedback Divider Paths
          1. 8.3.8.5.1 APLL1N Divider With SDM
          2. 8.3.8.5.2 APLL2N Divider With SDM
        6. 8.3.8.6  APLL Loop Filters (LF1, LF2)
        7. 8.3.8.7  APLL Voltage Controlled Oscillators (VCO1, VCO2)
          1. 8.3.8.7.1 VCO Calibration
        8. 8.3.8.8  APLL VCO Clock Distribution Paths (P1, P2)
        9. 8.3.8.9  DPLL Reference (R) Divider Paths
        10. 8.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 8.3.8.11 DPLL Loop Filter (DLF)
        12. 8.3.8.12 DPLL Feedback (FB) Divider Path
      9. 8.3.9  Output Clock Distribution
      10. 8.3.10 Output Channel Muxes
      11. 8.3.11 Output Dividers (OD)
      12. 8.3.12 Clock Outputs (OUTx_P/N)
        1. 8.3.12.1 AC-Differential Output (AC-DIFF)
        2. 8.3.12.2 HCSL Output
        3. 8.3.12.3 1.8V LVCMOS Output
        4. 8.3.12.4 Output Auto-Mute During LOL
      13. 8.3.13 Glitchless Output Clock Start-Up
      14. 8.3.14 Clock Output Interfacing and Termination
      15. 8.3.15 Output Synchronization (SYNC)
      16. 8.3.16 1PPS Input to Output Phase Alignment (PRIREF-to-OUT7 SYNC)
        1. 8.3.16.1 PRIREF-to-OUT7 SYNC Phase Calculation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Start-Up
        1. 8.4.1.1 Device Power-On Reset (POR)
        2. 8.4.1.2 PLL Start-Up Sequence
        3. 8.4.1.3 HW_SW_CTRL Pin Functionalities
        4. 8.4.1.4 Using the EEPROM
      2. 8.4.2 PLL Operating Modes
        1. 8.4.2.1 Free-Run Mode
        2. 8.4.2.2 Lock Acquisition
        3. 8.4.2.3 Locked Mode
        4. 8.4.2.4 Holdover Mode
      3. 8.4.3 Digitally-Controlled Oscillator (DCO) Mode
        1. 8.4.3.1 DCO Frequency Step Size
        2. 8.4.3.2 DCO Direct-Write Mode
    5. 8.5 Programming
      1. 8.5.1 Interface and Control
      2. 8.5.2 I2C Serial Communication
        1. 8.5.2.1 I2C Block Register Transfers
      3. 8.5.3 SPI Serial Communication
        1. 8.5.3.1 SPI Block Register Transfer
      4. 8.5.4 Register Map and EEPROM Map Generation
      5. 8.5.5 General Register Programming Sequence
      6. 8.5.6 EEPROM Programming Flow
        1. 8.5.6.1 EEPROM Programming Using Method #1 (Register Commit)
          1. 8.5.6.1.1 Write SRAM Using Register Commit
          2. 8.5.6.1.2 Program EEPROM
        2. 8.5.6.2 EEPROM Programming Using Method #2 (Direct Writes)
          1. 8.5.6.2.1 Write SRAM Using Direct Writes
          2. 8.5.6.2.2 User-Programmable Fields In EEPROM
      7. 8.5.7 Read SRAM
      8. 8.5.8 Read EEPROM
      9. 8.5.9 EEPROM Start-up Mode Default Configuration
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Start-Up Sequence
      2. 9.1.2 Power Down (PDN) Pin
      3. 9.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 9.1.3.1 Mixing Supplies
        2. 9.1.3.2 Power-On Reset (POR) Circuit
        3. 9.1.3.3 Powering Up From a Single-Supply Rail
        4. 9.1.3.4 Power Up From Split-Supply Rails
        5. 9.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 9.1.4 Slow or Delayed XO Start-Up
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Supply Bypassing
      2. 9.4.2 Device Current and Power Consumption
        1. 9.4.2.1 Current Consumption Calculations
        2. 9.4.2.2 Power Consumption Calculations
        3. 9.4.2.3 Example
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Reliability
        1. 9.5.3.1 Support for PCB Temperature up to 105°C
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TICS Pro
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.16 1PPS Input to Output Phase Alignment (PRIREF-to-OUT7 SYNC)

The LMK05318B contains an open-loop synchronization feature to provide phase determinism between a 1PPS PRIREF input clock and a 1PPS OUT7 output clock. The feature is also known as pseudo zero-delay mode (pseudo-ZDM). Phase determinism can occur when there is an input clock edge for every output clock edge. The PRIREF-to-OUT7 SYNC feature is used to align the OUT7 output clock edge with the PRIREF input for every sync event. If phase determinism is required for more than one output or for other frequencies besides 1PPS, consider designing with the LMK5B33216 or LMK5C33216A. Refer to the application note, Multi-Clock Synchronization for more details on synchronization.

The feature enables applications to meet stringent timing requirements, such as ITU-T G8273.2. Use the feature to synchronize the OUT7 clock with a 1PPS input and to minimize the input-to-output phase delay to within ± 1 VCO cycle. An aligned and deterministic phase relationship is achieved between a 1PPS input and 1PPS output through the open-loop sync shown in Figure 8-31.

LMK05318B 1PPS PRIREF to OUT7 Sync Diagram Figure 8-31 1PPS PRIREF to OUT7 Sync Diagram

When the DPLL is not locked and the DPLL reference input is invalid, the OUT7 clock is held in a mute state (no clock). Once the reference input is validated and selected, the OUT7 channel divider is reset or SYNCed using the DPLL reference input clock edge to achieve a phase relationship between the PRIREF and OUT7. When the PRIREF-to-OUT7 SYNC feature is enabled, the OUT7 clock is not affected by a global output SYNC event (R12[6]) and OUT[0:6] are not be affected by the PRIREF-to-OUT7 SYNC event.

To use the feature, the following must be considered.

  • The feature is recommended only for a 1PPS input frequency and 1PPS output frequency.
  • The feature is only available for the PRIREF input and not the SECREF input.
  • The feature is enabled by setting R252[7:6] = 0x3.
  • The OUT7 clock must be sourced from the BAW VCO.
  • The DPLL must be enabled and locked. If the DPLL loses lock and enters holdover, then the DPLL_LOOP_EN (R252[0]) must be toggled (1→0→1) upon holdover exit.