SNAS843C December   2024  – July 2025 CDC6C

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Environmental Compliance
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bulk Acoustic Wave (BAW)
      2. 8.3.2 Device Block-Level Description
      3. 8.3.3 Function Pin
      4. 8.3.4 Clock Output Interfacing and Termination
      5. 8.3.5 Temperature Stability
      6. 8.3.6 Mechanical Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Multiple Loads With a Single CDC6Cx
      2. 9.1.2 CDC6Cx CISPR25 Radiated Emission Performance
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Providing Thermal Reliability
        2. 9.4.1.2 Recommended Solder Reflow Profile
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Orderable Part Number Decoder

11 Revision History

Changes from Revision B (May 2025) to Revision C (July 2025)

  • Specified frequency stability for each package sizeGo
  • Specified available frequency stability orderable options per package sizeGo
  • Improve frequency stability (to ±25ppm) for DLE, DLF, and DLX packagesGo
  • Specified improved frequency stability for DLE, DLF, and DLX packagesGo

Changes from Revision A (January 2025) to Revision B (May 2025)

  • Updated the numbering formatting for tables, figures, and cross-references throughout the documentGo
  • Added legend to explain color assignment for Table 5-1 Go
  • Added output frequency used for all output rise and fall time dataGo
  • Added frequency stability for -40°C to 85°C temperature rangeGo
  • Combined random phase jitter to show jitter values based on output frequency range rather than specific output frequenciesGo
  • Changed 25MHz output to include random phase jitter from 12kHz to 20MHz offsetsGo
  • Removed integration bandwidth for RMS period jitterGo
  • Updated Figure 6-9 to include frequency offsets through 20MHzGo
  • Updated the Detailed Design Procedure to specify output frequency of 25MHz and corrected rise and fall times to match the Electrical Characteristics table.Go
  • Changed Figure 9-3 and Figure 9-4 to include frequency offsets through 20MHz.Go
  • Updated the Mechanical, Packaging, and Orderable Information sectionGo

Changes from Revision * (December 2024) to Revision A (January 2025)

  • Updated the numbering formatting for tables, figures, and cross-references throughout the documentGo