SNAS849A December   2024  – July 2026 LMX2624-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
        2. 6.3.7.2 Determining the VCO Gain
        3. 6.3.7.3 Double Buffering (Shadow Registers)
        4. 6.3.7.4 Watchdog Feature
        5. 6.3.7.5 RECAL Feature
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Phase Synchronization
        1. 6.3.13.1 General Concept
        2. 6.3.13.2 Categories of Applications for SYNC
        3. 6.3.13.3 Procedure for Using SYNC
      14. 6.3.14 SYSREF
        1. 6.3.14.1 Programmable Fields
        2. 6.3.14.2 Examples
        3. 6.3.14.3 SYSREF Procedure
      15. 6.3.15 Pin-Mode Integer Frequency Generation
        1. 6.3.15.1 4-level Pins Using GPIOs
        2. 6.3.15.2 Pin-Mode Example
      16. 6.3.16 Device Functional Modes
    4. 6.4 Treatment of Unused Pins
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
      3. 6.5.3 Register Maps
        1. 6.5.3.1 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 OSCin Configuration
      2. 7.1.2 OSCin Slew Rate
      3. 7.1.3 RF Output Buffer Power Control
      4. 7.1.4 RF Output Buffer
      5. 7.1.5 RF Output Treatment for the Complimentary Side
        1. 7.1.5.1 Single-ended Termination of Unused Output
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Footprint Example on PCB Layout
      4. 7.4.4 Radiation Environments
        1. 7.4.4.1 Total Ionizing Dose
        2. 7.4.4.2 Single Event Effect
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Engineering Samples
    2. 10.2 Package Option Addendum
    3. 10.3 Tape and Reel Information

6.3.15 Pin-Mode Integer Frequency Generation

The LMX2624-SP has Pin-mode option to generate fixed frequency output without any serial programming. The output frequency is generated based on the Pin setting in the Pin-mode option. The Integer N divider, Output Channel Divider, OUTMUXs and Input Reference Doubler can be set using the Pin-mode options.

Conditions to use a device in Pin-mode.:

  • Set the pin-mode using CDIVx pins. All pin combinations of CDIVx pins except when connected to GROUND is consider as Pin-mode. The SPI control cannot be used in Pin-mode. If CDIV2, CDIV1, and CDIV0 are tied to GROUND, the device is in SPI-mode.
  • The rise time for the supply needs to be <50ms.
  • Fractional Numerator and Denominator not available in Pin-mode, which means PLL can be used in Integer mode only.
  • CAL pin tied to VCC. CAL pin has to be toggled LOW to HIGH for frequency change from f1 to f2 in pin mode.

NDIVx and CDIVx pins are four level pins. Four level pins are used to get more number of division values with less number of pins which helps to reduce the overall package size. NDIVx has total of six pins and CDIVx has three pins. 6 pins of NDIVx (NDIV5, NDIV4, NDIV3, NDIV2, NDIV1, NDIV0) with four levels can create total of 46 combinations, which means 4096 values. Similarly CDIVx (CDIV2, CDIV1, CDIV0) with four level pins have total of 43 = 64 combinations. Due to the four level pins, 9 pins are sufficient instead of 18 pins for two level pins. The four levels of pin are VL, VML, VMH and VH as shows in Figure 6-10. Use three 10kΩ resistors across VCC and GROUND which have four levels including VCC, GROUND and two mid levels called VMH (Voltage Mid High) and VML (Voltage Mid Low).

LMX2624-SP Four Level Pins Implementation Figure 6-10 Four Level Pins Implementation

NDIVx provides total of 4096 integer divider options in Pin-mode. Numerator (PLL_NUM) and Denominator (PLL_DEN) are not available in Pin-mode for fractional PLL and is only possible through SPI-mode. The minimum value for N divider restriction for Pin-mode NDIVx values are similar to the SPI-mode option. Refer to Table 6-2 for the N divider minimum value setting. Based on the N-divider decimal value, each NDIVx pin setting can be calculated with equivalent base 4.

Table 6-16 NDIVx Pin-Mode N-Divider Values
NDIV5 NDIV4 NDIV3 NDIV2 NDIV1 NDIV0 N-DIVIDER VALUE
VL VL VL VL VL VL 0
VL VL VL VL VL VML 1
VL VL VL VL VL VMH 2
VL VL VL VL VL VH 3
VL VL VL VL VML VL 4
VL VL VL VL VML VML 5
VL VL VL VL VML VMH 6
VL VL VL VL VML VH 7
VL VL VL VL VMH VL 8
. . . . . . . . . . . .
VL VL VL VH VMH VH 59
VL VL VL VH VH VL 60
VL VL VL VH VH VML 61
VL VL VL VH VH VMH 62
. . . . . . . . . . . .
VH VH VH VH VH VL 4092
VH VH VH VH VH VML 4093
VH VH VH VH VH VMH 4094
VH VH VH VH VH VH 4095

All combinations of Channel Divider settings which are available in SPI-mode are also available in Pin-mode option using CDIVx pins. Refer to Table 6-17 for CDIVx settings in Pin-mode, CHDIV<4:0> settings in SPI-mode and the corresponding Channel Divider value. Based on the Channel Divider value needed, CDIV2, CDIV1, CDIV0 pins needed to be connected to one of the four levels.

Table 6-17 CDIVx Pin-Mode Divider Values
CDIV2 CDIV1 CDIV0 CHDIV<4:0> EQUIVALENT IN SPI MODE CHANNEL DIVIDER VALUE
VL VL VL 0 SPI mode
VL VML VL 1 2
VL VMH VL 2 4
VL VMH VH 3 6
VML VL VL 4 8
VML VL VH 5 12
VML VML VL 6 16
VML VML VH 7 24
VML VMH VL 8 32
VML VMH VH 9 48
VML VH VL 10 64
VML VH VH 11 96
VMH VL VL 12 128
VMH VL VH 13 192
VMH VML VL 14 256
VMH VML VH 15 384
VMH VMH VL 16 512
VMH VMH VH 17 768
VMH VH VL 18 1024
VMH VH VH 19 1536

OUTMUX2, OUTMUX1 and OUTMUX0 pins are used to select the RFOUTx based on Table 6-18.

Table 6-18 OUTMUX Settings
OUTMUX2 OUTMUX1 OUTMUX0 RFOUTA OUTPUT RFOUTB OUTPUT
0 0 0 Channel Divider Channel Divider
0 0 1 Channel Divider VCO
0 1 0 VCO Channel Divider
0 1 1 VCO VCO
1 0 0 Doubler Channel Divider
1 0 1 VCO Doubler
1 1 0 Doubler VCO
1 1 1 Doubler Doubler