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LMX2624-SP

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5MHz to 28GHz space-grade wideband synthesizer with phase synchronization and JESD204B support

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Data sheet

LMX2624-SP

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Data sheet Order now

Product details

Frequency (max) (MHz) 28000 Frequency (min) (MHz) 5 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Phase synchronization, Programmable output power, SYSREF support (Compliant to JESD204B standard), Space grade Current consumption (mA) 360 Integrated VCO Yes Operating temperature range (°C) 25 to 25 Rating Space Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 28000 Frequency (min) (MHz) 5 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -129 Features Phase synchronization, Programmable output power, SYSREF support (Compliant to JESD204B standard), Space grade Current consumption (mA) 360 Integrated VCO Yes Operating temperature range (°C) 25 to 25 Rating Space Lock time (µs) (typ) (s) Loop BW dependent
HTQFP (PAP) 64 144 mm² 12 x 12
  • SMD 5962R2321001PXE
    • Total ionizing dose 100Krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 75MeV-cm2/mg
    • Single event functional interrupt (SEFI) immune up to 75MeV-cm2/mg
  • Wide band frequency synthesizer : 5MHz to 28GHz output frequency
  • –101dBc/Hz phase noise at 100kHz offset with 24GHz carrier
  • 60fs RMS jitter at 24GHz (1kHz to 300MHz)
  • Programmable output power
  • PLL key specifications:
    • Figure of merit: –236dBc/Hz
    • Normalized 1/f noise: –129dBc/Hz
    • Up to 200MHz phase detector frequency
  • Synchronization of output phase across multiple devices
  • Independent mute pins for RFoutA and RFoutB with 200ns mute/unmute time
  • Support for SYSREF with 9ps resolution programmable delay
  • 3.3V single power supply operation
  • Pin-mode: Pin configurable N divider and output divider in Integer PLL mode
  • 10 × 10mm² 64 lead QFP package
  • Operating temperature range: –55°C to +125°C
  • Supported by PLLatinum™ Simulator design tool
  • SMD 5962R2321001PXE
    • Total ionizing dose 100Krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 75MeV-cm2/mg
    • Single event functional interrupt (SEFI) immune up to 75MeV-cm2/mg
  • Wide band frequency synthesizer : 5MHz to 28GHz output frequency
  • –101dBc/Hz phase noise at 100kHz offset with 24GHz carrier
  • 60fs RMS jitter at 24GHz (1kHz to 300MHz)
  • Programmable output power
  • PLL key specifications:
    • Figure of merit: –236dBc/Hz
    • Normalized 1/f noise: –129dBc/Hz
    • Up to 200MHz phase detector frequency
  • Synchronization of output phase across multiple devices
  • Independent mute pins for RFoutA and RFoutB with 200ns mute/unmute time
  • Support for SYSREF with 9ps resolution programmable delay
  • 3.3V single power supply operation
  • Pin-mode: Pin configurable N divider and output divider in Integer PLL mode
  • 10 × 10mm² 64 lead QFP package
  • Operating temperature range: –55°C to +125°C
  • Supported by PLLatinum™ Simulator design tool

The LMX2624-SP is a high performance wideband phase-locked loop (PLL) with integrated voltage controlled oscillator (VCO) and voltage regulators that can output any frequency from 5MHz and 28GHz. The VCO on this device covers an entire octave so the frequency coverage is complete down to 5MHz. The high performance PLL with a figure of merit of –236dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter.

The LMX2624-SP allows users to synchronize the output of multiple instances of the device. This means that deterministic phase can be obtained from a device in use cases including the one with fractional engine or output divider enabled. The device also adds support for either generating or repeating SYSREF (compliant to JESD204B/C standard), making the device designed for low-noise clock source for high-speed data converters.

This device is fabricated in Texas Instruments’ advanced BiCMOS process and is available in a 64-lead QFP plastic package.

The LMX2624-SP is a high performance wideband phase-locked loop (PLL) with integrated voltage controlled oscillator (VCO) and voltage regulators that can output any frequency from 5MHz and 28GHz. The VCO on this device covers an entire octave so the frequency coverage is complete down to 5MHz. The high performance PLL with a figure of merit of –236dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter.

The LMX2624-SP allows users to synchronize the output of multiple instances of the device. This means that deterministic phase can be obtained from a device in use cases including the one with fractional engine or output divider enabled. The device also adds support for either generating or repeating SYSREF (compliant to JESD204B/C standard), making the device designed for low-noise clock source for high-speed data converters.

This device is fabricated in Texas Instruments’ advanced BiCMOS process and is available in a 64-lead QFP plastic package.
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Technical documentation

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* Data sheet LMX2624-SP 5MHz to 28GHz Wideband Synthesizer With Phase Synchronization and JESD204B/C Support datasheet PDF | HTML 13 Dec 2024
Application brief Allan Deviation Measurement Data from LMX2615 26 Jun 2025
Application brief Full Assist Feature in LMX2624 27 May 2025
Selection guide TI Space Products (Rev. K) 04 Apr 2025

Design & development

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Evaluation board

LMX2624SPEVM — LMX2624-SP evaluation module

LMX2624-SP evaluation module (EVM) is used to evaluate the performance of the LMX2624-SP device. This device is a space grade RF synthesizer in 10mm x 10mm 64-pin plastic package. LMX2624-SP is able to generate continuous wave signal up to 26GHz. This EVM provides a hardware interface to enable (...)

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Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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HTQFP (PAP) 64 Ultra Librarian
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