SNAS849B December   2024  – September 2026 LMX2624-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
        2. 6.3.7.2 Determining the VCO Gain
        3. 6.3.7.3 Double Buffering (Shadow Registers)
        4. 6.3.7.4 Watchdog Feature
        5. 6.3.7.5 RECAL Feature
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Phase Synchronization
        1. 6.3.13.1 General Concept
        2. 6.3.13.2 Categories of Applications for SYNC
        3. 6.3.13.3 Procedure for Using SYNC
      14. 6.3.14 SYSREF
        1. 6.3.14.1 Programmable Fields
        2. 6.3.14.2 Examples
        3. 6.3.14.3 SYSREF Procedure
      15. 6.3.15 Pin-Mode Integer Frequency Generation
        1. 6.3.15.1 4-level Pins Using GPIOs
        2. 6.3.15.2 Pin-Mode Example
      16. 6.3.16 Device Functional Modes
    4. 6.4 Treatment of Unused Pins
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
      3. 6.5.3 Register Maps
        1. 6.5.3.1 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 OSCin Configuration
      2. 7.1.2 OSCin Slew Rate
      3. 7.1.3 RF Output Buffer Power Control
      4. 7.1.4 RF Output Buffer
      5. 7.1.5 RF Output Treatment for the Complimentary Side
        1. 7.1.5.1 Single-ended Termination of Unused Output
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Footprint Example on PCB Layout
      4. 7.4.4 Radiation Environments
        1. 7.4.4.1 Total Ionizing Dose
        2. 7.4.4.2 Single Event Effect
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2 Detailed Design Procedure

When the frequencies are known, the loop filter must be designed. The integration of phase noise over a certain bandwidth (jitter) is an performance specification that translates to signal-to-noise ratio. Phase noise inside the loop bandwidth is dominated by the PLL, while the phase noise outside the loop bandwidth is dominated by the VCO. Generally, jitter is lowest if the loop bandwidth is designed to the point where the two intersect. A higher phase margin loop filter design has less peaking at the loop bandwidth and thus lower jitter. The trade-off with this is that longer lock times and spurs must be considered in design as well.

The PLLatinum Sim software is very useful in designing the loop filter and is available on the TI website. Using this tool, the results in Table 7-56 are obtained.

Table 7-2 PLLatinum Sim Results
COMPONENT VALUE UNIT
C1 390 pF
C2 68 nF
C3 1.8 nF
R2 68.1 Ω
R3 18.2 Ω

The TICS Pro software is very useful in calculating the necessary register values and configuring the device. Figure 7-4 shows the TICS Pro configuration for 12GHz output at RFoutA channel.

LMX2624-SP LMX2624-SP TICS Pro Setup Figure 7-4 LMX2624-SP TICS Pro Setup