SNAS849B December   2024  – September 2026 LMX2624-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
        2. 6.3.7.2 Determining the VCO Gain
        3. 6.3.7.3 Double Buffering (Shadow Registers)
        4. 6.3.7.4 Watchdog Feature
        5. 6.3.7.5 RECAL Feature
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Phase Synchronization
        1. 6.3.13.1 General Concept
        2. 6.3.13.2 Categories of Applications for SYNC
        3. 6.3.13.3 Procedure for Using SYNC
      14. 6.3.14 SYSREF
        1. 6.3.14.1 Programmable Fields
        2. 6.3.14.2 Examples
        3. 6.3.14.3 SYSREF Procedure
      15. 6.3.15 Pin-Mode Integer Frequency Generation
        1. 6.3.15.1 4-level Pins Using GPIOs
        2. 6.3.15.2 Pin-Mode Example
      16. 6.3.16 Device Functional Modes
    4. 6.4 Treatment of Unused Pins
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
      3. 6.5.3 Register Maps
        1. 6.5.3.1 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 OSCin Configuration
      2. 7.1.2 OSCin Slew Rate
      3. 7.1.3 RF Output Buffer Power Control
      4. 7.1.4 RF Output Buffer
      5. 7.1.5 RF Output Treatment for the Complimentary Side
        1. 7.1.5.1 Single-ended Termination of Unused Output
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Footprint Example on PCB Layout
      4. 7.4.4 Radiation Environments
        1. 7.4.4.1 Total Ionizing Dose
        2. 7.4.4.2 Single Event Effect
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

3.2V ≤ VCC ≤ 3.45V, –55°C ≤ TC ≤ +125°C., OSCIN = 100MHz, SM Clock = 12.5MHz,  Typical values are at VCC = 3.3V, 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
ICC Supply current (VCO output selected on both channels; RFOUTA enabled, RFOUTB disabled) OUTA_PD = 0, OUTB_PD = 1
OUTA_MUX = 1
OUTA_PWR = 7, CPG = 7
fOSC = fPD = 100MHz, fVCO = fOUT = 14.5GHz		 460 mA
Supply current (VCO output both RFOUTA and RFOUTB enabled) OUTA_PD = 0, OUTB_PD = 0
OUTA_MUX = 1, OUTB_MUX = 1
OUTA_PWR = 7, OUTB_PWR = 7, CPG = 7
fOSC = fPD = 100MHz, fVCO = fOUT = 14.5GHz		 660 mA
Supply current (channel divider selected on both channels; RFOUTA enabled, RFOUTB disabled) OUTA_PD = 0, OUTB_PD = 1,
OUTA_MUX = 0
OUTA_PWR = 7, CPG = 7
fOSC = fPD = 100MHz, fVCO = 15GHz, fOUT = 7.5GHz		 510
Supply current (channel divider both RFOUTA and RFOUTB enabled) OUTA_PD = 0, OUTB_PD = 0
OUTA_MUX = 0, OUTB_MUX = 0,
OUTA_PWR = 7, OUTB_PWR = 7, CPG = 7
fOSC = fPD = 100MHz, fVCO = 15GHz, fOUT = 7.5GHz		 685
Supply current (Doubler output selected on both channels; RFOUTA enabled, RFOUTB disabled) OUTA_PD = 0, OUTB_PD = 1,
OUTA_MUX = 2,
OUTA_PWR = 7, CPG = 7
fOSC = fPD = 100MHz, fVCO = 12GHz, fOUT = 24GHz		 650
Supply current (Doubler output on both RFOUTA and RFOUTB enabled) OUTA_PD = 0, OUTB_PD = 0
OUTA_MUX = 2, OUTB_MUX = 2,
OUTA_PWR = 7, OUTB_PWR = 7, CPG = 7
fOSC = fPD = 100MHz, fVCO = 12GHz, fOUT = 24GHz		 730
Supply current (Doubler output on RFOUTA and CHDIV on RFOUTB enabled) OUTA_PD = 0, OUTB_PD = 0
OUTA_MUX = 2, OUTB_MUX = 0,
OUTA_PWR = 7, OUTB_PWR = 7, CPG = 7
fOSC = fPD = 100MHz, fVCO = 12GHz
fOUTA = 24GHz, fOUTB = 6GHz		 810
Power on reset current RESET = 1 (Device wake-up) 250
Power down current POWERDOWN = 1 17
OUTPUT CHARACTERISTICS
Fout RF output frequency 5 30000 MHz
pOUT Single-ended output power(2)(4)
OUTx_PWR = 7; Doubler output		 fOUT = 30GHz 1.2 dBm
Differential output power(5) 4.2
Single-ended output power(2)(4) fOUT = 27GHz 2
Differential output power(5) 5
Single-ended output power(2)(4) fOUT = 24GHz 3.5
Differential output power(5) 6.5
Single-ended output power(2)(4) fOUT = 18GHz 2
Differential output power(5) 5
Single-ended output power(2)(4)
OUTx_PWR = 7; VCO output		 fOUT = 15GHz 2.5
Differential output power(5) 5.5
Single-ended output power(2)(4) fOUT = 7.5GHz 6
Differential output power(5) 9
Single-ended output power(2)(4)
OUTx_PWR = 7; Divider output		 fOUT = 4GHz 6.5
Differential output power(5) 9.5
H1/2 1/2 Harmonic, single ended measurement Measured at 12GHz frequency Fout = 2 × Fvco = 24GHz –55 dBc
1/2 Harmonic, differential ended –60
1/2 Harmonic, single ended measurement Measured at 8GHz frequency Fout = 2 × Fvco = 16GHz –42
1/2 Harmonic, differential ended –45
H3/2 3/2 Harmonic, single ended measurement Measured at 24GHz frequency Fout = 2 × Fvco = 16GHz –45
3/2 Harmonic, differential ended measurement –45
Pmute Single-ended output power leakage when output is muted Fout = 24GHz –40 dBm
Single-ended output power leakage when output is muted Fout = 12GHz –55
Single-ended output power leakage when output is muted Fout = 6GHz; RFoutA & RFoutB configured for CHDIV and both muted –85
Single-ended output power leakage when output is muted Fout = 6GHz; RFoutA & RFoutB configured for CHDIV; RFoutA muted; measured at RFoutA –60
tMUTE Mute enable time Fout = 12GHz 200 ns
tUNMUTE Mute disable time Fout = 12GHz 200
isoCH Channel to channel isolation (Doubler to VCO) RFOUTA = 24GHz; RFOUTB = 12GHz −39 dBc
Channel to channel isolation (VCO to CH divider) RFOUTA = 12GHz; RFOUTB = 6GHz −53
Channel to channel isolation (Doubler to CH divider) RFOUTA = 24GHz; RFOUTB = 6GHz −41
Phase Noise RF Output Frequency Phase Noise Fout = 24GHz 1kHz −92.5 dBc/Hz
10kHz −102
100kHz −104
1MHz −112.5
10MHz −138
100MHz −150.7
Fout = 15GHz 1kHz −97
10kHz −105.5
100kHz −107.5
1MHz −115
10MHz −140
100MHz −156
Jitter RMS Jitter Fout = 24GHz, fOSCin = 100MHz, fPD = 200MHz; Integration range 1kHz to 100MHz 54 fs
Skew Skew between RFOUTA and RFOUTB RFOUTA = RFOUTB = 16GHz 32 ps
RFOUTA = RFOUTB = 8GHz 6
RFOUTA = RFOUTB = 4GHz 5
INPUT SIGNAL PATH
fOSCin Reference input frequency OSC_2X = 0 5 1200 MHz
OSC_2X = 1 5 200
vOSCin Reference input voltage Single-ended AC coupled sine wave input with complementary side AC coupled to ground with 50Ω resistor fOSCin ≥ 20MHz 0.4 2 VPP
10MHz ≤ fOSCin < 20MHz 0.8 2
5MHz ≤ fOSCin < 10MHz 1.6 2
PHASE DETECTOR AND CHARGE PUMP
fPD Phase detector frequency(1) MASH_ORDER = 0 0.125 250 MHz
MASH_ORDER > 0 5 200 MHz
ICPout Charge-pump leakage current CPG = 0 15 nA
Effective charge pump current. This is the sum of the up and down currents CPG = 4 3 mA
CPG = 1 6
CPG = 5 9
CPG = 3 12
CPG = 7 15
PNPLL_1/f Normalized PLL 1/f noise fPD = 100MHz, fVCO = 12GHz(3) –129 dBc/Hz
PNPLL_FOM Normalized PLL noise floor fPD = 100MHz, fVCO = 12GHz(3) –236
VCO CHARACTERISTICS
fVCO VCO frequency 7500 15000 MHz
PNVCO VCO phase noise VCO1
fVCO = 8.1GHz		 100kHz –106 dBc/Hz
1MHz –129
10MHz –148
100MHz –158
VCO2
fVCO = 9.3GHz		 100kHz –104
1MHz –126
10MHz –143
100MHz –157
VCO3
fVCO = 10.4GHz		 100kHz –102
1MHz –126
10MHz –142
100MHz –157
VCO4
fVCO = 11.4GHz		 100kHz –99
1MHz –124
10MHz –145
100MHz –156
VCO5
fVCO = 12.5GHz		 100kHz –99
1MHz –123
10MHz –143
100MHz –156
VCO6
fVCO = 13.6GHz		 100kHz –98
1MHz –122
10MHz –142
100MHz –157
VCO7
fVCO = 14.7GHz		 100kHz –97
1MHz –121
10MHz –141
100MHz –156
tVCOCAL VCO calibration time Switch across the entire frequency band; fOSC = fPD = 100MHz; No assist calibration 650 µs
tLockTime Lock time  Full Assist mode, Loop Bandwidth = 300KHz, PFD Frequency = 100MHz; RFOUTA from 9.5GHz to 9.52GHz, 1PPM settling around RFOUT; Double buffering enabled 16 µs
KVCO VCO Gain 8.1GHz 94 MHz/V
9.3GHz 106
10.4GHz 122
11.4GHz 148
12.5GHz 185
13.6GHz 202
14.7GHz 233
|ΔTCL| Allowable temperature drift when VCO is not re-calibrated Device configured in SPI mode 125 °C
H2 VCO second harmonic fVCO = 8GHz, divider disabled; Single-ended output –30 dBc
H3 VCO third harmonic fVCO = 8GHz, divider disabled; Single-ended output −14
DIGITAL INTERFACE (Applies to SCK, SDI, CSB, CAL, RECAL_EN, MUXout, SYNC, SysRefReq, REF_DBLR_EN, MuteX, OUTMUXx)
VIH High-level input voltage 1.6 V
VIL Low-level input voltage 0.4
IIH High-level input current 100 µA
IIL Low-level input current –100
VOH High-level output voltage MUXout pin Load current = –5mA VCC – 0.6 V
VOL Low-level output voltage MUXout pin Load current = 5mA 0.6
VSysRefCM SYSREF Output Common mode voltage OUTB_PWR = 7; VCC = 3.3V; Differential 100 Ω load 2.1 V
VSysRef SYSREF Output Swing OUTB_PWR = 7; VCC = 3.3V; Differential 100 Ω load 1.2
fSysRef SYSREF Frequency range 187.5 MHz
fSysRefDly SYSREF delay step size fInterpolator = 800MHz 9 ps
VL CDIV0, CDIV1, CDIV2 Voltage levels 0 0.4 V
VML CDIV0, CDIV1, CDIV2 Voltage levels 0.8 VCC/3 1.4
VMH CDIV0, CDIV1, CDIV2 Voltage levels 1.9 2×VCC/3 2.5
VH CDIV0, CDIV1, CDIV2 Voltage levels 3 VCC 3.45
VL NDIV0, NDIV1, NDIV2, NDIV3, NDIV4, NDIV5 Voltage levels 0 0.4
VML NDIV0, NDIV1, NDIV2, NDIV3, NDIV4, NDIV5 Voltage levels 0.8 VCC/3 1.4
VMH NDIV0, NDIV1, NDIV2, NDIV3, NDIV4, NDIV5 Voltage levels 1.9 2×VCC/3 2.5
VH NDIV0, NDIV1, NDIV2, NDIV3, NDIV4, NDIV5 Voltage levels 3 VCC 3.45
(1) For lower VCO frequencies, the N divider minimum value can limit the phase-detector frequency.
(2) Single-ended output power at device pin. Trace losses are de-embedded. Unused port terminated to 50Ω load.
(3) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20× log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_1/f + 20 × log(Fvco / 1GHz) – 10× log(offset / 10kHz). After these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 × log(10 PLL_Flat / 10 + 10 PLL_flicker /10 )
(4) Output power, spurs, and harmonics can vary based on board layout and components.
(5) Differential output power measured with external Balun. Balun and Trace losses are de-embedded.