SNAS901 September   2025 CDCLVP111-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Fanout Buffer for Line Card Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 LVPECL Output Termination
          2. 8.2.1.2.2 Input Termination
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information

8.2.1.3 Application Curves

The following plots are example phase noise plots before and after using the CDCLVP111-SEP. The CDCLVP111-SEP clock buffer adds fs (typical) of jitter from 12kHz to 20MHz for a 2.4GHz output. More frequency phase noise plots shown below.

CDCLVP111-SEP SMA100A Reference Phase Noise, 82fs, 100MHz (12kHz to 20MHz)
Figure 8-10 SMA100A Reference Phase Noise, 82fs, 100MHz (12kHz to 20MHz)
CDCLVP111-SEP SMA100A Reference Phase Noise, 62fs, 200MHz (12kHz to 20MHz)
Figure 8-12 SMA100A Reference Phase Noise, 62fs, 200MHz (12kHz to 20MHz)
CDCLVP111-SEP SMA100A Reference Phase Noise, 22fs, 1GHz (12kHz to 20MHz)
Figure 8-14 SMA100A Reference Phase Noise, 22fs, 1GHz (12kHz to 20MHz)
CDCLVP111-SEP SMA100A Reference Phase Noise, 22fs, 2.4GHz (12kHz to 20MHz)
Figure 8-16 SMA100A Reference Phase Noise, 22fs, 2.4GHz (12kHz to 20MHz)
CDCLVP111-SEP CDCLVP111-SEP Output Phase Noise, 155fs additive jitter, 100MHz (12kHz to 20MHz)
Figure 8-11 CDCLVP111-SEP Output Phase Noise, 155fs additive jitter, 100MHz (12kHz to 20MHz)
CDCLVP111-SEP CDCLVP111-SEP Output Phase Noise, 88fs additive jitter, 200MHz (12kHz to 20MHz)
Figure 8-13 CDCLVP111-SEP Output Phase Noise, 88fs additive jitter, 200MHz (12kHz to 20MHz)
CDCLVP111-SEP CDCLVP111-SEP Output Phase Noise, 20fs additive jitter, 1GHz (12kHz to 20MHz)
Figure 8-15 CDCLVP111-SEP Output Phase Noise, 20fs additive jitter, 1GHz (12kHz to 20MHz)
CDCLVP111-SEP CDCLVP111-SEP Output Phase Noise, 13fs, 2.4GHz (12kHz to 20MHz)
Figure 8-17 CDCLVP111-SEP Output Phase Noise, 13fs, 2.4GHz (12kHz to 20MHz)