SNAS901 September   2025 CDCLVP111-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Fanout Buffer for Line Card Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 LVPECL Output Termination
          2. 8.2.1.2.2 Input Termination
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information

4 Pin Configuration and Functions

Figure 4-1 CDCLVP111-SEP VFP Package 32-Pin LQFP Top ViewCDCLVP111-SEP
Table 4-1 Pin Functions
PIN Type DESCRIPTION
NAME NO.
CLK_SEL(1) 2 Input Clock select. Used to select between CLK0 and CLK1 input pairs. LVTTL/LVCMOS functionality compatible.
CLK0(1) 3 Input Positive differential LVECL/LVPECL input pair
CLK0(2) 4 Input Negative differential LVECL/LVPECL input pair
CLK1(1) 6 Input Positive differential LVECL/LVPECL input pair
CLK1(2) 7 Input Negative differential LVECL/LVPECL input pair
Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 11, 13, 15, 18, 20, 22, 24, 27, 29, 31 Output LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn.
Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 10, 12, 14, 17, 19, 21, 23, 26, 28, 30 Output LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn.
VBB 5 Power Reference voltage output for single-ended input operation
VCC 1, 9, 16, 25, 32 Power Supply voltage
VEE 8 Power Device ground or negative supply voltage in ECL mode
Thermal Pad DAP No Connect Can be connected to VEE or left floating. Pad is electrically floating.
(1) CLK_SEL and CLKn pulldown resistor = 75kΩ
(2) CLKn pullup resistor = 37.5kΩ and pull down resistor = 50kΩ.