SNAS935B March   2025  – November 2025 CDC6C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Environmental Compliance
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bulk Acoustic Wave (BAW)
      2. 8.3.2  Device Block-Level Description
      3. 8.3.3  Function Pin
      4. 8.3.4  Clock Output Interfacing and Termination
      5. 8.3.5  CDC6Cx-Q1 CISPR25 Radiated Emission Performance
        1. 8.3.5.1 EMI Reduction and Slow Mode Options
      6. 8.3.6  Temperature Stability
      7. 8.3.7  Frequency Aging
      8. 8.3.8  Mechanical Robustness
      9. 8.3.9  Wettable Flanks
      10. 8.3.10 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Multiple Loads With a Single CDC6Cx-Q1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Providing Thermal Reliability
        2. 9.4.1.2 Recommended Solder Reflow Profile
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Orderable Part Number Decoder

8.3.5.1 EMI Reduction and Slow Mode Options

For EMI reduction, the CDC6Cx-Q1 has orderable options to reduce slew rate and increase rise and fall times. Slowing down the sharp rising and falling edges of a clock output, or lowering the output slew rate, decreases high-frequency harmonics, thereby lessening EMI. For applications requiring lesser EMI, select the appropriate rise and fall time options and see the CDC6Cx-Q1 CISPR25 Radiated Emission Performance Report for more EMI reduction strategies.

The CDC6Cx-Q1 has four slow mode options other than the normal mode. Based on the desired rise and fall times, select the right slow mode option and load capacitance value. Table 8-2 shows the minimum recommended capacitance for each slow mode.

Table 8-2 Minimum Recommended Capacitance per Slow Mode
SLOW MODE MINIMUM RECOMMENDED CAPACITANCE (pF)
Slow Mode 1 2
Slow Mode 2 5
Slow Mode 3 10
Slow Mode 4 15

Table 8-3 has recommended slow mode options for various load capacitance for a 25MHz output clock. For example, with load capacitance 15pF, Slow Mode 4 option results in the slowest rise and fall times. You can also select Slow Mode 1, Slow Mode 2, or Slow Mode 3 with 15pF but the rise and fall times are faster.

Table 8-3 Rise / Fall Time Options (25MHz Output)
SLOW MODE OPTION LOAD CAPACITANCE RISE AND FALL TIME (ns) WITH SLOW MODE (TYP / MAX) RISE AND FALL TIME (ns) WITH NORMAL MODE (TYP / MAX)
Slow Mode 1 2pF 0.81 / 1.06 0.62 / 1.01
Slow Mode 2 5pF 1.47 / 1.62 0.76 / 1.24
Slow Mode 3 10pF 2.44 / 2.61 1.4 / 1.7
Slow Mode 4 15pF 3.29 / 3.5 1.88 / 2.11