SNAS935C March   2025  – July 2026 CDC6C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Environmental Compliance
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bulk Acoustic Wave (BAW)
      2. 8.3.2  Device Block-Level Description
      3. 8.3.3  Function Pin
      4. 8.3.4  Clock Output Interfacing and Termination
      5. 8.3.5  CDC6Cx-Q1 CISPR25 Radiated Emission Performance
        1. 8.3.5.1 EMI Reduction and Slow Mode Options
      6. 8.3.6  Temperature Stability
      7. 8.3.7  Frequency Aging
      8. 8.3.8  Mechanical Robustness
      9. 8.3.9  Wettable Flanks
      10. 8.3.10 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Multiple Loads With a Single CDC6Cx-Q1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Providing Thermal Reliability
        2. 9.4.1.2 Recommended Solder Reflow Profile
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.4.2 Layout Examples

Figure 9-10 shows the printed circuit board (PCB) layout examples as done on the evaluation module (EVM) for the CDC6Cx-Q1.

CDC6C-Q1 PCB Layout Example From CDC6 EVM Figure 9-10 PCB Layout Example From CDC6 EVM
CDC6C-Q1 PCB Layout Example From CDC6 EVM - Top Layer Figure 9-11 PCB Layout Example From CDC6 EVM - Top Layer
CDC6C-Q1 PCB Layout Example From CDC6 EVM - GND Layer Figure 9-12 PCB Layout Example From CDC6 EVM - GND Layer
CDC6C-Q1 PCB Layout Example From CDC6 EVM - Power Layer Figure 9-13 PCB Layout Example From CDC6 EVM - Power Layer
CDC6C-Q1 PCB Layout Example From CDC6 EVM - Bottom Layer Figure 9-14 PCB Layout Example From CDC6 EVM - Bottom Layer