SNLA239C May   2021  – December 2023 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS , DP83869HM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Standards and System Requirements
    1. 1.1 Standards
    2. 1.2 Test Equipment Suppliers
    3. 1.3 Test System Requirements
    4. 1.4 Software Setup and Installation
  5. 2Ethernet Physical Layer Compliance Testing
    1. 2.1 Standard Test Setup and Procedures
    2. 2.2 1000BASE-T
      1. 2.2.1 Test Mode 1
        1. 2.2.1.1 Template
        2. 2.2.1.2 Peak Voltage
        3. 2.2.1.3 Droop
      2. 2.2.2 Test Mode 2
        1. 2.2.2.1 Jitter Master Unfiltered
      3. 2.2.3 Test Mode 4
        1. 2.2.3.1 Distortion
        2. 2.2.3.2 Common-Mode Voltage
        3. 2.2.3.3 Return Loss
    3. 2.3 100BASE-TX
      1. 2.3.1 Template (Active Output Interface)
      2. 2.3.2 Differential Output Voltage
      3. 2.3.3 Signal Amplitude Symmetry
      4. 2.3.4 Rise and Fall Time
      5. 2.3.5 Waveform Overshoot
      6. 2.3.6 Jitter
      7. 2.3.7 Duty Cycle Distortion
      8. 2.3.8 Return Loss
    4. 2.4 10BASE-Te
      1. 2.4.1 Link Pulse
      2. 2.4.2 10Base-Te Standard
        1. 2.4.2.1 TP_IDL
        2. 2.4.2.2 MAU, Internal
        3. 2.4.2.3 Jitter With TPM
        4. 2.4.2.4 Jitter Without TPM
        5. 2.4.2.5 Differential Voltage
        6. 2.4.2.6 Common-Mode Voltage
        7. 2.4.2.7 Return Loss
        8. 2.4.2.8 Harmonic Content
  6. 3Debug Test Methods
  7. 4References
  8. 5Revision History
  9.   A Outline of Ethernet Compliance Tests for DP8386x
  10.   B Ethernet Compliance Testing MDIO Register Writes for DP8386x

B Ethernet Compliance Testing MDIO Register Writes for DP8386x

1000 Base Test Mode 1:
Reg 0x1F = 0x8000//Reset PHY
Reg 0x9 = 0x3B00//Test Mode 1
Reg 0x25 = 0x480//Output test mode to all channels
Reg 0x1D5 = 0xF508

//Increases VoD swing. This register can be applied on the other test scripts as well as in end use-case applications.

Reg 0x1F = 0x4000

//Restart PHY

1000 Base Test Mode 2:
Reg 0x1F = 0x8000//Reset PHY
Reg 0x9 = 0x5B00//Test Mode 2
Reg 0x25 = 0x480//Output test mode to all channels
Reg 0x1F = 0x4000//Restart PHY
1000 Base Test Mode 4:
Reg 0x1F = 0x8000//Reset PHY
Reg 0x9 = 0x9B00//Test Mode 4
Reg 0x25 = 0x400//Single channel selection. It is important to change to appropriate channel under test
//400: Channel A
//420: Channel B
//440: Channel C
//460: Channel D
Reg 0x1F = 0x4000//Restart PHY
100 Base Standard:
Reg 0x1F = 0x8000//Reset PHY
Reg 0x0 = 0x2100//Programs DUT to 100Base-TX Mode
Reg 0x10 = 0x5008//Programs DUT to Forced MDI or MDIX mode (0x5028)
Reg 0x1F = 0x4000//Restart PHY
10 Base Link Pulse:
Reg 0x1F = 0x8000//Reset PHY
Reg 0x0 = 0x100//Programs DUT to 10Base-Te Mode
Reg 0x10 = 0x5008//Programs DUT to Forced MDI Mode or MDIX mode (0x5028)
Reg 0x1F = 0x4000//Restart PHY
10 Base Standard:
Reg 0x1F = 0x8000//Reset PHY
Reg 0x0 = 0x100//Programs DUT to 10Base-Te Mode
Reg 0x10 = 0x5008//Programs DUT to Forced MDI Mode or MDIX mode (0x5028)
Reg 0x16 = 0xD004//Programs DUT to generate traffic
Reg 0x1F = 0x4000//Restart PHY