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DP83867CR

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Low-power, robust gigabit Ethernet PHY transceiver in a small QFN package

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Data sheet
Low-power, robust gigabit Ethernet PHY transceiver in a small QFN package

DP83867CR

ACTIVE
Data sheet Order now

Product details

Datarate (Mbps) 10/100/1000 Interface type RGMII Number of ports Single Rating Catalog Features Cable diagnostics, IEEE 1588 SOF, JTAG1149.1 Supply voltage (V) 1 and 2.5 IO supply (Typ) (V) 1.8, 2.5, 3.3 Operating temperature range (C) 0 to 70 Cable length (m) 130
Datarate (Mbps) 10/100/1000 Interface type RGMII Number of ports Single Rating Catalog Features Cable diagnostics, IEEE 1588 SOF, JTAG1149.1 Supply voltage (V) 1 and 2.5 IO supply (Typ) (V) 1.8, 2.5, 3.3 Operating temperature range (C) 0 to 70 Cable length (m) 130
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VQFN (RGZ) 48 49 mm² 7 x 7
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  • Ultra low RGMII latency TX < 90ns, RX < 290ns
  • Time Sensitive Network (TSN) compliant
  • Low power consumption 457 mW
  • Exceeds 8000 V IEC 61000-4-2 ESD protection
  • Meets EN55011 class B emission standards
  • 16 programmable RGMII delay modes on RX/TX
  • Integrated MDI termination resistors
  • Programmable MII/GMII/RGMII termination impedance
  • WoL (Wake-on-LAN) packet detection
  • 25-MHz or 125-MHz synchronized clock output
  • IEEE 1588 time stamp support
  • RJ45 mirror mode
  • Fully compatible to IEEE 802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T Specification
  • Cable diagnostics
  • MII, GMII and RGMII MAC interface options
  • Configurable I/O voltage (3.3 V, 2.5 V, 1.8 V)
  • Fast link drop mode
  • JTAG support
  • Ultra low RGMII latency TX < 90ns, RX < 290ns
  • Time Sensitive Network (TSN) compliant
  • Low power consumption 457 mW
  • Exceeds 8000 V IEC 61000-4-2 ESD protection
  • Meets EN55011 class B emission standards
  • 16 programmable RGMII delay modes on RX/TX
  • Integrated MDI termination resistors
  • Programmable MII/GMII/RGMII termination impedance
  • WoL (Wake-on-LAN) packet detection
  • 25-MHz or 125-MHz synchronized clock output
  • IEEE 1588 time stamp support
  • RJ45 mirror mode
  • Fully compatible to IEEE 802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T Specification
  • Cable diagnostics
  • MII, GMII and RGMII MAC interface options
  • Configurable I/O voltage (3.3 V, 2.5 V, 1.8 V)
  • Fast link drop mode
  • JTAG support
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The DP83867 device is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. Optimized for ESD protection, the DP83867 exceeds 8-kV IEC 61000-4-2 (direct contact).

The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly to twisted pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit Media Independent Interface (GMII) or Reduced GMII (RGMII). The QFP package supports MII/GMII/RGMII whereas the QFN package supports RGMII.

The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low latency and provides IEEE 1588 Start of Frame Detection.

The DP83867 consumes only 490mW (PAP) and 457mW (RGZ) under full operating power. Wake on LAN can be used to lower system power consumption.

The DP83867 device is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. Optimized for ESD protection, the DP83867 exceeds 8-kV IEC 61000-4-2 (direct contact).

The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly to twisted pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit Media Independent Interface (GMII) or Reduced GMII (RGMII). The QFP package supports MII/GMII/RGMII whereas the QFN package supports RGMII.

The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low latency and provides IEEE 1588 Start of Frame Detection.

The DP83867 consumes only 490mW (PAP) and 457mW (RGZ) under full operating power. Wake on LAN can be used to lower system power consumption.

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Pin-for-pin with same functionality to the compared device.
DP83867CS ACTIVE Low-power, robust gigabit Ethernet PHY transceiver with SGMII This product supports SGMII MII and operates over a commercial temperature range of 0°C to 70°C
DP83867IR ACTIVE Industrial temperature, robust gigabit Ethernet PHY transceiver This product supports RGMII MII an operates over an industrial temperature range of -40°C to 85°C
DP83869HM ACTIVE Extended temperature, high-immunity gigabit Ethernet PHY transceiver with copper & fiber interface This product supports Cu & fiber, RGMII & SGMII and operates over a high-temperature range of -40°C to 125°C

Technical documentation

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Type Title Date
* Data sheet DP83867IR/CR Robust, High Immunity 10/100/1000 Ethernet Physical Layer Transceiver datasheet (Rev. F) 17 Oct 2019
Application note How to Pass IEEE Ethernet Compliance Tests 20 Sep 2021
Application note Ethernet PHY PCB Design Layout Checklist 01 Jun 2021
Application note How to Configure DP838XX for Ethernet Compliance and Loopback Testing (Rev. B) 07 May 2021
Application note 88E1512 to DP83867 and DP83869 System Rollover 30 Aug 2019
Application note AR8031 to DP83867 and DP83869 System Rollover 30 Aug 2019
Application note Importance of Latency in Factory Automation (Rev. A) 06 Feb 2019
Application note Selection and specification of crystals for Texas Instruments ethernet physical 06 Feb 2019
Application note KSZ9031RN to DP83867CR/CS/E/IR/IS System Rollover 12 Sep 2016
Application note DP83867 Troubleshooting Guide (Rev. A) 06 Apr 2016
User guide USB-2-MDIO User's Guide 19 Feb 2016
Application note RGMII Interface Timing Budgets 28 Oct 2015
Application note How to Configure DP83867 Start of Frame 27 Oct 2015
Application note DP83867E/IS/CS/IR/CR RGZ Power Consumption Data 07 Oct 2015
Application note AN-1469 PHYTER® Design & Layout Guide (Rev. D) 26 Apr 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DP83867ERGZ-R-EVM — DP83867ERGZ RGMII 1000M/100M/10M Ethernet PHY evaluation module

The DP83867ERGZ-R-EVM supports 1000/100/10BASE and is compliant with the IEEE 802.3 standard. This reference design supports the RGMII MAC interface.

The DP83867ERGZ-R-EVM evaluation module (EVM) for the DP83867 device includes 3 on-board status LEDs and 5-V connectors with (...)

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Application software & framework

USB-2-MDIO — USB to MDIO serial management tool

The USB-2-MDIO software tool lets Texas Instruments' Ethernet PHYs access the MDIO status and device control registers.  The USB-2-MDIO tool includes a LaunchPad™ Development kit for TI's MSP430™ MCUs that is interfaced with a lightweight (...)
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Driver or library

ETHERNET-SW — Ethernet PHY Linux drivers & tools

The Linux drivers for Texas Instruments' Ethernet physical layer (PHY) transceivers support communication through the serial management interface (MDC/MDIO) to configure and read PHY registers.

The USB-2-MDIO software lets you directly access the registers during debug and (...)

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Simulation model

DP83867IR IBIS Model (Rev. A)

SNLM191A.ZIP (80 KB) - IBIS Model
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Simulation model

DP83867 QFN BSDL Model (Rev. A)

SNLM201A.ZIP (5 KB) - BSDL Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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Reference designs

TIDA-050034 — Integrated power supply reference design for NXP i.MX 7D processor

TIDA-050034 is a fully functional development board combining a TI PMIC, TPS65218DO, with NXP i.MX 7Dual Application Processor.

The hardware design consists of DDR3L SDRAM (2x512MB), 64MB Serial NOR Flash, 8GB eMMC 5.0 iNAND, SD Card interface v3.0, 50 pin LCD Connector for external TFT display (...)

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Reference designs

TIDEP-01008 — Multi-sensor platform reference design on Jacinto™ ADAS processors

The multi-sensor platform reference design for Advanced Driver Assistance Systems (ADAS) from D3 Engineering provides qualified developers with a fully functioning evaluation platform for testing and development of ADAS applications, for use primarily in the automotive industry.  D3 also (...)
document-generic Schematic
Reference designs

TIDA-00204 — EMI/EMC Compliant Industrial Temp Dual Port Gigabit Ethernet PHY Reference Design

This design allows for performance evaluation of two industrial grade DP83867IR Gigabit Ethernet PHYs and Sitara™ host processors with integrated Ethernet MAC and Switch. It was developed to meet industrial requirements for EMI and EMC. The application firmware implements a driver for the (...)
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Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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