Extended temperature, robust low-latency gigabit Ethernet PHY transceiver with SGMII
Product details
Parameters
Package | Pins | Size
Features
- Extra low latency TX < 90 ns, RX < 290 ns
- Time Sensitive Network (TSN) compliant
- Low power consumption: 457 mW
- Exceeds 8000 V IEC 61000-4-2 ESD protection
- Meets EN55011 class B emission standards
- 16 programmable RGMII delay modes on RX/TX
- Integrated MDI termination resistors
- Programmable MAC interface termination impedance
- WoL (Wake-on-LAN) packet detection
- 25-MHz or 125-MHz synchronized clock output
- IEEE 1588 time stamp support
- RJ45 mirror mode
- Fully compatible to IEEE 802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T Specification
- Cable diagnostics
- RGMII and SGMII MAC interface options
- Configurable I/O voltage (3.3 V, 2.5 V, 1.8 V)
- Fast link drop mode
- JTAG support
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Description
The DP83867 device is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. Optimized for ESD protection, the DP83867 exceeds 8-kV IEC 61000-4-2 (direct contact).
The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly to twisted pair media through an external transformer. This device interfaces directly to the MAC layer through Reduced GMII (RGMII) or embedded clock Serial GMII (SGMII).
The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low latency and provides IEEE 1588 Start of Frame Detection.
Designed for low power, the DP83867 consumes only 457 mW under full operating power. Wake-on-LAN can be used to lower system power consumption.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The DP83867ERGZ-R-EVM supports 1000/100/10BASE and is compliant with the IEEE 802.3 standard. This reference design supports the RGMII MAC interface.
The DP83867ERGZ-R-EVM evaluation module (EVM) for the DP83867 device includes 3 on-board status LEDs and 5-V connectors with onboard (...)
Features
- 1000BASE-Tx IEEE 802.3 compliant
- Meets EN55011 3m Class B emissions and immunity requirements
- SFD IEEE 1588 timestamp
- Wake-on LAN
- Low power modes: Active sleep, passive sleep, IEEE power down and deep power down
Description
The DP83867ERGZ-S-EVM supports 1000/100/10BASE and is compliant with the IEEE 802.3 standard. This reference design supports SGMII MAC interface.
The DP83867 EVM includes three onboard status LEDs, 5V connectors with onboard LDOs, and is JTAG accessible. The DP83867 EVM is capable of providing a (...)
Features
- 1000 Base-Tx IEEE 802.3 Compliant
- Meets EN55011 3m Class B Emissions and Immunity requirements
- SFD IEEE 1588 timestamp
- Wake-on-LAN
- Low power modes: Active Sleep, Passive Sleep, IEEE Power Down, and Deep Power Down
Description
Features
- 66AK2G02 C66x DSP + ARM Cortex A15 Processor at 600 MHz
- Two programmable real-time unit (PRU) and industrial communication subsystems (PRU-ICSS)
- PCI express 2.0 with integrated PHY
- Gigabit ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connector
- Four 10x100 industrial ethernet connectors
- (...)
Software development
Features
- MDIO bus controller
- IEEE 802.3 clause 22
- IEEE 802.3ah clause 22 access to clause 45 registers
The USB-2-MDIO software lets you directly access the registers during debug and prototyping. (...)
Design tools & simulation
Reference designs
Design files
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| VQFN (RGZ) | 48 | View options |
Ordering & quality
Support & training
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Training series
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TI Precision Labs - Ethernet: What is an Ethernet PHY?
Get a quick overview of Ethernet physical layer transceivers, also called PHYs.
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