Product details


Datarate (Mbps) 10/100/1000 Interface type RGMII, SGMII Number of ports Single Rating Catalog Features Cable diagnostics, IEEE 1588 SOF, JTAG1149.1 Supply voltage (V) 1 and 2.5 IO supply (Typ) (V) 1.8, 2.5, 3.3 Operating temperature range (C) 0 to 70 Cable length (m) 130 open-in-new Find other Ethernet PHYs

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other Ethernet PHYs


  • Extra low latency TX < 90 ns, RX < 290 ns
  • Time Sensitive Network (TSN) compliant
  • Low power consumption: 457 mW
  • Exceeds 8000 V IEC 61000-4-2 ESD protection
  • Meets EN55011 class B emission standards
  • 16 programmable RGMII delay modes on RX/TX
  • Integrated MDI termination resistors
  • Programmable MAC interface termination impedance
  • WoL (Wake-on-LAN) packet detection
  • 25-MHz or 125-MHz synchronized clock output
  • IEEE 1588 time stamp support
  • RJ45 mirror mode
  • Fully compatible to IEEE 802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T Specification
  • Cable diagnostics
  • RGMII and SGMII MAC interface options
  • Configurable I/O voltage (3.3 V, 2.5 V, 1.8 V)
  • Fast link drop mode
  • JTAG support

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The DP83867 device is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. Optimized for ESD protection, the DP83867 exceeds 8-kV IEC 61000-4-2 (direct contact).

The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly to twisted pair media through an external transformer. This device interfaces directly to the MAC layer through Reduced GMII (RGMII) or embedded clock Serial GMII (SGMII).

The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low latency and provides IEEE 1588 Start of Frame Detection.

Designed for low power, the DP83867 consumes only 457 mW under full operating power. Wake-on-LAN can be used to lower system power consumption.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 16
Type Title Date
* Datasheet DP83867E/IS/CS Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver datasheet (Rev. C) Oct. 17, 2019
Technical articles Top 3 considerations for harsh industrial Ethernet Nov. 04, 2019
Application notes 88E1512 to DP83867 and DP83869 System Rollover Aug. 30, 2019
Application notes AR8031 to DP83867 and DP83869 System Rollover Aug. 30, 2019
Application notes Importance of Latency in Factory Automation (Rev. A) Feb. 06, 2019
Application notes Selection and specification of crystals for Texas Instruments ethernet physical Feb. 06, 2019
Application notes Configuring Ethernet Devices With 4-Level Straps (Rev. A) Sep. 27, 2018
Application notes How to Configure DP838XX for Ethernet Compliance and Loopback Testing (Rev. A) Jan. 31, 2017
Application notes KSZ9031RN to DP83867CR/CS/E/IR/IS System Rollover Sep. 12, 2016
User guides DP83867E SGMII EVM Users Guide May 13, 2016
Application notes DP83867 Troubleshooting Guide (Rev. A) Apr. 06, 2016
User guides USB-2-MDIO User's Guide Feb. 19, 2016
Application notes RGMII Interface Timing Budgets Oct. 28, 2015
Application notes How to Configure DP83867 Start of Frame Oct. 27, 2015
Application notes DP83867E/IS/CS/IR/CR RGZ Power Consumption Data Oct. 07, 2015
Application notes AN-1469 PHYTER® Design & Layout Guide (Rev. D) Apr. 26, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The DP83867ERGZ-R-EVM supports 1000/100/10BASE and is compliant with the IEEE 802.3 standard. This reference design supports the RGMII MAC interface.

The DP83867ERGZ-R-EVM evaluation module (EVM) for the DP83867 device includes 3 on-board status LEDs and 5-V connectors with onboard (...)

  • 1000BASE-Tx IEEE 802.3 compliant
  • Meets EN55011 3m Class B emissions and immunity requirements
  • SFD IEEE 1588 timestamp
  • Wake-on LAN
  • Low power modes: Active sleep, passive sleep, IEEE power down and deep power down
document-generic User guide

The DP83867ERGZ-S-EVM supports 1000/100/10BASE and is compliant with the IEEE 802.3 standard. This reference design supports SGMII MAC interface.

The DP83867 EVM includes three onboard status LEDs, 5V connectors with onboard LDOs, and is JTAG accessible. The DP83867 EVM is capable of providing a (...)

  • 1000 Base-Tx IEEE 802.3 Compliant
  • Meets EN55011 3m Class B Emissions and Immunity requirements
  • SFD IEEE 1588 timestamp
  • Wake-on-LAN
  • Low power modes: Active Sleep, Passive Sleep, IEEE Power Down, and Deep Power Down
document-generic User guide
The K2G Industrial Communications Engine (ICE) enables 66AK2Gx processor developers to immediately start development, demonstration and test of industrial communication protocols for products such as PLC, bus controllers, motion control and other real-time industrial networked applications.  (...)
  • 66AK2G02 C66x DSP + ARM Cortex A15 Processor at 600 MHz
  • Two programmable real-time unit (PRU) and industrial communication subsystems (PRU-ICSS)
  • PCI express 2.0 with integrated PHY
  • Gigabit ethernet port supporting 10/100/1000 Mbps data rate on RJ45 connector
  • Four 10x100 industrial ethernet connectors
  • (...)

Software development

USB to MDIO serial management tool
USB-2-MDIO The USB-2-MDIO software tool lets Texas Instruments' Ethernet PHYs access the MDIO status and device control registers.  The USB-2-MDIO tool includes a LaunchPad™ Development kit for TI's MSP430™ MCUs that is interfaced with a lightweight (...)
  • MDIO bus controller
  • IEEE 802.3 clause 22
  • IEEE 802.3ah clause 22 access to clause 45 registers
Ethernet PHY Linux drivers & tools
ETHERNET-SW The Linux drivers for Texas Instruments' Ethernet physical layer (PHY) transceivers support communication through the serial management interface (MDC/MDIO) to configure and read PHY registers.

The USB-2-MDIO software lets you directly access the registers during debug and prototyping.  (...)

Design tools & simulation

SNLM191A.ZIP (80 KB) - IBIS Model
SNLM201A.ZIP (5 KB) - BSDL Model
SNLM211.ZIP (5409 KB) - IBIS-AMI Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

Reference designs

EMI/EMC Compliant Industrial Temp Dual Port Gigabit Ethernet PHY Reference Design
TIDA-00204 This design allows for performance evaluation of two industrial grade DP83867IR Gigabit Ethernet PHYs and Sitara™ host processors with integrated Ethernet MAC and Switch. It was developed to meet industrial requirements for EMI and EMC. The application firmware implements a driver for the PHY (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

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Ordering & quality

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