SNLA267A March   2019  – June 2019 DS90UB953-Q1 , DS90UB954-Q1 , DS90UB960-Q1

 

  1.   How to Design a FPD-Link III System Using DS90UB953-Q1 and DS90UB954-Q1
    1.     Trademarks
    2. 1 Overview
      1. 1.1 System Level Functionality
    3. 2 Basic Design Rules
      1. 2.1 IDX and MODE Pin Verification
        1. 2.1.1 REF Clock, CLK IN, AON and Frequency Selection
          1. 2.1.1.1 Synchronous Mode
          2. 2.1.1.2 Non-Synchronous CLK_IN Mode
          3. 2.1.1.3 Non-Synchronous AON Mode
          4. 2.1.1.4 CSI Throughput
          5. 2.1.1.5 Clocking and Frequency Selection Example
      2. 2.2 Successful I2C Communication With 953 and 954
        1. 2.2.1 Aliasing
        2. 2.2.2 Port Selection on 954
      3. 2.3 I2C Passthrough Verification
      4. 2.4 Basic Diagnostic and Error Registers
    4. 3 Designing the Link Between SER and DES
      1. 3.1 Back Channel Configuration
      2. 3.2 BIST
        1. 3.2.1 BIST Configuration and Status
        2. 3.2.2 BIST Procedure
        3. 3.2.3 List of Registers Used in BIST Script
      3. 3.3 AEQ
      4. 3.4 CML Out
    5. 4 Designing Link Between SER and Image Sensor
      1. 4.1 Sensor Initialization Using SER GPIOs
      2. 4.2 CLKOUT
    6. 5 Designing Link Between DES and ISP
      1. 5.1 Frame Sync
        1. 5.1.1 Using SER GPIOs From the DES
        2. 5.1.2 Internal and External Frame Sync Configuration
        3. 5.1.3 Tables for Using GPIOs and Frame Sync
      2. 5.2 Port Forwarding
      3. 5.3 Pattern Generation
        1. 5.3.1 Accessing Indirect Registers
        2. 5.3.2 Pattern Generation From DES to ISP and SER to DES
    7. 6 Hardware Design
      1. 6.1 Basic I2C Connectors
        1. 6.1.1 I2C Pullups for SDA and SCL
      2. 6.2 AC Capacitor on FPD3 Link
      3. 6.3 Capacitance Used in Loop Filter
      4. 6.4 Critical Signal Routing
      5. 6.5 Time Domain Reflection
      6. 6.6 Return Loss and Insertion Loss
      7. 6.7 Power-over-Coax (PoC)
      8. 6.8 Voltage and Temperature Sensing
    8. 7 Appendix
      1. 7.1 Scripts
        1. 7.1.1  BIST Script
        2. 7.1.2  Example Sensor Initialization Script
        3. 7.1.3  CSI Enable and Port Forwarding Script
        4. 7.1.4  Enabling CMLOUT FPD3 RX Port 0 on 954
        5. 7.1.5  Remote Enabled SER GPIO Toggle Script
        6. 7.1.6  Local SER GPIO Toggle Script
        7. 7.1.7  Internal FrameSync on 953 GPIO1
        8. 7.1.8  External FrameSync on 953 GPIO0
        9. 7.1.9  SER GPIOs as Inputs and Output to DES GPIO
        10. 7.1.10 Pattern Generation on the 953 Script
        11. 7.1.11 Pattern Generation on the 954 Script
        12. 7.1.12 Monitor Errors for Predetermined Time Script
        13. 7.1.13 954 and 953 CSI Register Check Script
        14. 7.1.14 Time Till Lock Script on 953
      2. 7.2 Acknowledgments
  2.   Revision History

2.4 Basic Diagnostic and Error Registers

This section discusses the various errors and registers used in 953 and 954 systems. Various errors will be presented and discussed using basic definitions. The various registers pertaining to the errors are found in the tables below. More information regarding these registers can be found in the data sheet.

Parity Errors: Parity errors refer to errors that occur over the forward channel. These errors are caused by irregular changes to data, as it is recorded when it is entered in memory. Note that these errors only have to do with the link between the SER and DES (found in Section 3), which means they are independent of CSI errors. Check addresses 0x55, 0x56, and 0x4D on the 954.

Cyclic Redundancy Check (CRC) Errors: CRC errors refer to errors that occur over the back channel. These errors are caused by accidental changes to the data. The redundancy in the transmitted data is checked and flagged. Note that these errors only have to do with the link between the SER and DES (found in Section 3), which means they are independent of CSI errors. Check addresses 0x4D on the 954 and 0x55 and 0x56 on the 953.

BIST CRC Errors: BIST CRC Errors refer to errors generated during the Built-In Self Test (BIST) between the 954 and 953. Note that these errors only have to do with the link between the SER and DES (found in Section 3), which means they are independent of CSI errors. For more information about BIST, refer to Section 3.2. Check addresses.

CSI Errors: CSI errors refer to errors in CSI data packets. These can be Checksum, Length, or ECC errors. CSI errors can occur across any of the links, however, they usually occur when designing the link between the DES and ISP (found in Section 5) is designed.

CSI Checksum Errors: CSI Checksum errors refer to an error detected in the packet data portion of the CSI packet.

CSI Length Errors: CSI length errors refer to an error detected in expected packet length. Packet length errors occur if the data length field in the packet header does not match the actual data length for the packet.

CSI Error Correcting Code (ECC) Errors: CSI ECC errors refer to errors in CSI data packets that are 1 or 2 bits off from their correct value. Errors that are 1 bit, are automatically corrected while errors that are 2 bits are detected but not corrected.

FPD III Encoder Error: FPD III Encoder error refers to errors in the FPD-Link III encoding that has been detected by the receiver. These are also tied to the Link error count and Link error threshold.

Buffer Error: Buffer errors refer to the overflow condition that has occurred on the packet buffer FIFO.

Table 10. DS90UB954-Q1 Registers Used for Diagnostics and Checking Errors

DEVICE REGISTER NUMBER REGISTER NAME REGISTER DESCRIPTION
954 0x04 DEVICE_STS General flags of device status and communication between DES and SER: check sum config, power up initialization, refclk valid, pass, lock
954 0x05 PAR_ERR_THOLD_HI Parity error threshold high byte that provides 8 most bits of threshold value. Flagged in RX_PORT_STS1
954 0x06 PAR_ERR_THOLD_LO Parity error threshold low byte that provides 8 most bits of threshold value. Flagged in RX_PORT_STS1
954 0x4D RX_PORT_STS1 Flags for various detected errors: BCC CRC error, Lock status Change, BCC sequencing error, Parity Error, Pass, and Lock
954 0x4E RX_PORT_STS2 Flags for various detected errors: Line Length Unstable, Line Length changed, FPD3 Encoder error, packet buffer error, CSI Error, frequency stable, FPD3 CLK detect, Line count change
954 0x55 RX_PAR_ERR_HI 8 MSBs of FPD3 Parity Errors
954 0x56 RX_PAR_ERR_LO 8 LSBs of FPD3 Parity Errors
954 0x57 BIST_ERR_COUNT Returns BIST error count
954 0x7A CSI_RX_STS Has general flags for CSI errors: Packet length, check sum, 2-bit ECC, 1-bit ECC
954 0x7B CSI_ERR_COUNTER Returns counts number of CSI packets received with errors
954 0xB9 LINK_ERROR_COUNT Enables serial link data integrity error count, link error count threshold, and waiting for SFLITER to stabilize
954 0xD0 PORT_DEBUG Indicates SER is in BIST mode. If not SER is not in BIST and bit [5] is high, could indicate error
954 0x24 INTERRUPT_STS If interrupt enabled, flags when and where interrupts occurred: global interrupt, CSI Transmit port 0, RX port 1 and port 0
954 0x36-0x37 CSI_TX_ICR, CSI_TX_ISR Detects CSI RX errors and enables interrupts if necessary
954 0xD8-0xDB PORT_ICR_LO, PORT_ICR_HI, PORT_ISR_HI, and PORT_ISR_LO Interrupts on various errors: see the 954 data sheet register table for more information

Table 11. DS90UB953-Q1 Registers Used for Diagnostics and Checking Errors

DEVICE REGISTER NUMBER REGISTER NAME REGISTER DESCRIPTION
953 0x49 BC_CTRL Back channel control used for clearing CRC and BIST errors and TX-RX link detect timer value
953 0x52 GENERAL_STS General flags that indicate status of errors (BCC, BIST CRC, CRC, Link Lost) and communication between DES and SER
953 0x54 BIST_ERR_CN1 8 bits that count the CRC errors in BIST mode
953 0x55 CRC_ERR_CNT1 CRC Error count (LSB)
953 0x56 CRC_ERR_CNT2 CRC Error count (MSB)
953 0x5C CSI_ERR_CNT Counts number of CSI packets received with errors since the last read of the counter
953 0x5D CSI_ERR_STATUS Shows Line Length mismatch, Check sum error, ECC 2-bit error detected, ECC 1-bit Error Detect
953 0x5E CSI_ERR_DLANE01 Shows errors for lanes 0 and 1: single bit error in sync, multi error in sync, control error in HS request Mode
953 0x5F CSI_ERR_DLANE23 Shows errors for lanes 2 and 3: single bit error in sync, multi error in sync, control error in HS request Mode
953 0x60 CSI_ERR_CLK_LANE CLK Lane: control error in HS request mode, Invalid LP state detected
953 0x79 BCC_STATUS Error flags over BCC: master timeout, slave error, slave time out, and SER Response
953 0x77 ECC_ERR_SEL Choose to force many different ECC errors