SNLA364C March 2021 – June 2022 DP83TD510E
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:14 | Reserved | R | 0x0 | |
| 13 | PRBS_Sync_Loss | R/WoC | 0x0 |
1b = PRBS has locked 0b = PRBS has not locked |
| 12 | Pkt_Done | R | 0x0 | Set when all MAC packets with CRC are transmitted |
| 11 | Pkt_Gen_Busy | R | 0x0 |
1b = Packet generator is in process 0b = Packet generator is not in process |
| 10 | PRBS_Pkt_Ov | R | 0x0 |
If set, packet counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit[1] of 0x011F |
| 9 | PRBS_Byte_Ov | R | 0x0 |
If set, bytes counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit[1] of 0x011F |
| 8 | PRBS_Lock | R | 0x0 |
1b = PRBS checker is locked (sync) on received byte stream 0b = PRBS checker is not locked |
| 7:0 | PRBS_Err_Cnt | R | 0x0 |
Holds number of errored bits received by the PRBS checker Value in this register is locked when write is done to bit[0] or bit[1] When PRBS Count Mode set to zero, count stops on 0xFF Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters |