SNLA364C March   2021  – June 2022 DP83TD510E

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 1-V and 2.4-V p2p Mode Scripts
  5. 3 Time-Domain Reflectometry
    1. 3.1 TDR Application Startup
      1. 3.1.1 TDR_CFG (Address = 0x001E) [Reset = 0x0000]
      2. 3.1.2 TDR_Fault_Status (Address = 0x030C) [Reset = 0x0000]
    2. 3.2 TDR Test Procedure
  6. 4 Active Link Cable Diagnostics
    1. 4.1 ALCD Application Startup
    2. 4.2 ALCD Test Procedure
      1. 4.2.1 Cable Calibration
      2. 4.2.2 Cable Quality Measurement
  7. 5 Signal Quality Indicator
    1. 5.1 SQI Application Startup
      1. 5.1.1 MSE Detection (Address = 0x0A85 ) [Reset = 0x0000]
    2. 5.2 SQI Test Procedure
  8. 6 Cable Diagnostics Summary
  9. 7 Loopback Modes
    1. 7.1 BISCR (Address = 0x0016) [Reset = 0x0100]
  10. 8 Pseudo-Random Bit Sequence Functions
    1. 8.1 PRBS_CFG_1 (Address = 0x0119) [Reset = 0x0574]
    2. 8.2 PRBS_STATUS_4 (Address = 0x011F) [Reset = 0x0000]
  11. 9 USB to MDIO Procedure
  12. 10IEEE 802.3cg PMA Compliance
  13. 11Revision History

7 Loopback Modes

There are several loopback options within the DP83TD510E that test and verify various functional blocks within the PHY. Enabling loopback modes allow for in-circuit testing of the digital and analog data paths. The DP83TD510E may be configured to any one of the Near-End Loopback modes or to the Far-End (reverse) Loopback mode. MII Loopback is configured using the Control Register (BMCR, address 0x0000). All other loopback modes are enabled using the BIST Control Register (BISCR, address 0x0016).

GUID-8096911C-020C-4D4F-95D8-6D78F36753F8-low.gifFigure 7-1 Loopback Test Modes