SNLA364C March 2021 – June 2022 DP83TD510E
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:13 | Reserved | R | 0x0 | |
| 12 | Send_Packet | R/W | 0x0 | Enables generating MAC packet with fix/incremental data w CRC (pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear) Cleared automatically when pkt_done is set |
| 11 | Reserved | R | 0x0 | |
| 10:8 | CFG_PRBS_CHK_SEL | R/W | 0x5 |
000: Checker receives from RGMII TX 010: Checker receives from RMII TX 011: Checker receives from MII TX 101: Checker receives from Cu RX |
| 7 | Reserved | R | 0x0 | |
| 6:4 | CFG_PRBS_GEN_SEL | R/W | 0x7 |
000: PRBS transmits to RGMII RX 010: PRBS transmits to RMII RX 011: PRBS transmits to MII RX 101: PRBS transmits to Cu TX |
| 3 |
CFG_PRBS_CNT_Mode | R/W |
0x0 |
1b = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again 0b = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting. |
| 2 | CFG_PRBS_CHK_Enable | R/W | 0x1 | Enable PRBS checker xbar (to receive data). Must be enabled for packet counters to work |
| 1 | CFG_PKT_GEN_PRBS | R/W | 0x0 |
If bit[1] is set: (a) When pkt_gen_en is set, PRBS packets are generated continuously (b) When pkt_gen_en is cleared, PRBS RX checker is still enabled If bit [1] is cleared: (a) When pkt_gen_en is set, non - PRBS packet is generated (b) When pkt_gen_en is cleared, PRBS RX checker is disabled as well |
| 0 | PKT_GEN_Enable | R/W | 0x0 |
1b = Enable packet/PRBS generator 0b = Disable packet/PRBS generator |