SNLA423A March   2023  – June 2025 DP83826E , DP83826I

 

  1.   1
  2.   Trademarks
  3. 1DP83826 Application Overview
  4. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS and CEXT
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface Signals (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
          1. 2.2.6.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  5. 3Summary
  6. 4References
  7. 5Revision History

2.2.5 Probe the Strap Pins During Initialization

The PHY has strap pins which assist with configuring the device in a predetermined mode. The voltage at these pins is the sole determining factor as to whether or not the device is in one mode or the other.

The expectation during the sampling time for strapping is that the external strap network (consisting of a PU or PD resistor, if applicable) along with the internal resistor creates a voltage divider in which the PHY samples. No other component on the line need to affect the DC bias set by this network.

DP83826 DP83826 Strap Circuit Figure 2-5 DP83826 Strap Circuit
DP83826 DP83826 LED Strap Circuit Figure 2-6 DP83826 LED Strap Circuit
DP83826 DP83826 Enhanced Strap Flowchart Figure 2-7 DP83826 Enhanced Strap Flowchart

However, in some cases, other devices on the board (for example, the MAC) will pull or drive these pins unexpectedly. The strap values can be read from the registers. The values are available in Reg 0x0467 (SOR1) and Reg 0x0468 (SOR2). If there is power cycle dependency to an issue, the strapping may be marginal and can be observed cycle to cycle against these registers to determine if the PHY is strapped in an unintended state.

Measurements can be made during power up and after power up when the RESET_N signal is asserted.