SNLA423A March   2023  – June 2025 DP83826E , DP83826I

 

  1.   1
  2.   Trademarks
  3. 1DP83826 Application Overview
  4. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS and CEXT
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface Signals (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
          1. 2.2.6.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  5. 3Summary
  6. 4References
  7. 5Revision History

2.2.6.1 Read and Check Register Values

If applicable, Station Management Interface can be useful in providing valuable status fields during a debug. However, verify that this communication is accurate to avoid compounding issues. Make sure that MDIO has a pull up resistor to VDDIO as this pin is an open-drain to the PHY. When idle, the voltage needs to be VDDIO. Make sure the SMI access follows the following sequence:

DP83826 SMI Read Operation Figure 2-8 SMI Read Operation
DP83826 SMI Write Operation Figure 2-9 SMI Write Operation

Read the registers and verify the default values shown in the data sheet. Note that the initial values of some registers can vary based on strap options. The expected register values for PHY operation and link in 10/100 Mbps with auto-negotiation enabled are shown in Table 2-4.

Table 2-4 DP83826 Register Value References
REGISTER ADDRESSREGISTER VALUEComments
10 Mbps100 Mbps
0x000031003100Auto-Negotiation Control, MII Loopback
0x0001786D786DLink Status
0x0003A131A131

PHY Revision

A111 = Basic

A131 = Enhanced

0x0004004101E1DUT 10/100Mbps advertisement
0x0005 141E141E1LP 10/100Mbps advertisement
0x000A01000100Odd Nibble Detection (EtherCAT)
0x000B00000000Fast Link Drop Configuration
0x0010 24717 or 00174715 or 0715PHY Status
0x001101080108PWDN/INT
0x001400000000False Carrier Counter
0x001500000000RX Error Counter
0x001700410041RMII Configuration
0x0019C000CC00MDI(x) Configuration

With the PHY linked in a given speed, use these values as a reference to identify any variance from the expected operation. Note that not all registers need to be the same, for example:

(1) The value of Reg 0x0005 depends on the link partner's capabilities.
(2) The difference in the MSB of Reg 0x0010 is due to [14], does not affect anything. The significant difference is the 7 or 5 as the LSB, this tells the Speed Status.

Example: After powering and linking the PHY in 10 Mbps, Reg 0x10 is read at Reg 0x17. Meaning Bits [4, 2, 1, 0] are high. These bits confirm: Auto-Negotiation is complete, Full-Duplex, 10 Mbps Mode, and valid link established.

Repeating this process for any values distinct from the expected values shown in Table 2-4 help diagnose the exact state of the PHY for any encountered issues.