SNLA423A March   2023  – June 2025 DP83826E , DP83826I

 

  1.   1
  2.   Trademarks
  3. 1DP83826 Application Overview
  4. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS and CEXT
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface Signals (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
          1. 2.2.6.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  5. 3Summary
  6. 4References
  7. 5Revision History

2.4.2 RMII Check

Reduced Media Independent Interface, as specified in the RMII specification v1.2, provides a reduced pin count alternative to the IEEE 802.3 MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII. The DP83826 offers two types of RMII operations: RMII Leader and RMII Follower.

In RMII Leader operation, the DP83826 operates from either a 25MHz CMOS-level oscillator connected to XI pin or a 25MHz crystal connected across XI and XO pins. A 50MHz output clock referenced from DP83826 should be connected to the MAC.

In RMII Follower operation, the DP83826 operates from a 50MHz CMOS-level oscillator connected to the XI pin and shares the same clock as the MAC. Alternatively, the PHY can operate from a 50MHz clock provided by the Host MAC.

The RMII specification has the following characteristics:

  • Supports 100BASE-TX and 10BASE-Te
  • Single clock reference sourced from the MAC to PHY (or from an external source)
  • Provides independent 2-bit wide transmit and receive data paths
  • Uses CMOS signal levels, the same levels as the MII interface

RMII can be set with pulling up Hardware Strap 8 RX_D2 = 1. Reg 0x0467[8] can confirm the Status of Strap 8 (High or Low) and Reg 0x0468, can confirm the PHY's MAC Mode(MII = 0 | RMII = 1).

In this mode, data transfers are 2 bits for every clock cycle using the internal 50MHz reference clock for both transmit and receive paths. The RMII signals are summarized below:

Table 2-13 RMII Signals
FUNCTIONPINS
Receive data linesTX_D[1:0]
Transmit data linesRX_D[1:0]
Receive control signalTX_EN
Transmit control signalCRS_DV
DP83826 RMII Follower Signaling - MAC Follower Configuration Figure 2-16 RMII Follower Signaling - MAC Follower Configuration
DP83826 RMII Follower Signaling - MAC Leader Configuration Figure 2-17 RMII Follower Signaling - MAC Leader Configuration
DP83826 RMII Leader Signaling Figure 2-18 RMII Leader Signaling

Data on TX_D[1:0] are latched at the PHY with reference to the 50MHz-clock in RMII Leader mode and Follower mode. Data on RX_D[1:0] is provided in reference to 50MHz clock. In addition, CRX_DV can be configured as RX_DV signal. This allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication.

CH 1 (RMII 50MHz Clock), CH 2 (RX_D0)

DP83826 RMII Clock and Data Figure 2-19 RMII Clock and Data