SNLA431 User guide

SNLA431 January 2024 DP83TC812R-Q1 , DP83TC812S-Q1

4.9 Power Up Timing

Meeting the power up timing requirements given in the data sheet is imperative for correct operation of the PHY. Failure to meet the power up timing requirements can lead to an inability to achieve link, read and write issues, or a completely non-operational PHY. Given below are the power up and reset timing requirements for the DP83TC812. Measure each of the following items on an oscilloscope to verify that every item is met.

Supply ramps start from 0V. Supply ramps are continuous and smooth (no pedestal voltages).
Ramp time is greater than 0.2ms and less than 8ms.
Oscillator is stable within 10ms of power ramp. Measure CLKOUT pin on one channel and supply ramp on another.
MDC toggling does not occur within 10ms of supply ramp or within 1ms of reset pin de-assertion.

Table 4-6 Power Up Timing Specifications

PARAMETER		MIN	NOM	MAX	UNIT
T5.1	Supply ramp time: For all supplies	0.2		0.8	ms
T5.3	XTAL Startup / Settling: Powerup to XI good/stabilized		0.35		ms
T5.4	Oscillator stabilization time from power up			10	ms
T5.5	Post power-up to SMI ready: Post Power-up wait time required before MDC preamble can be sent for register access	10			ms
T5.6	Power-up to Strap latch-in			10	ms
T5.7	CLKOUT Startup/Settling: Powerup to CLKOUT good/stabilized			10	ms
T5.8	Power-up to idle stream			10	ms

Figure 4-5 Power Up Timing Diagram

Table 4-7 Reset Timing Specifications

PARAMETER		MIN	NOM	MAX	UNIT
T6.1	Reset Pulse Width: Minimum Reset pulse width to be able to reset	720			us
T6.2	Reset to SMI ready: Post reset wait time required before MDC preamble can be sent for register access	1			ms
T6.3	Reset to Strap latch-in: Hardware configuration pins transition to output drivers		40		us
T6.4	Reset to idle stream			1800	us

Figure 4-6 Reset Timing Diagram