SNLA437A December   2023  – October 2025 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826I

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83822 Application Overview
  5. 2Troubleshooting the PHY Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Power Supply Ramp Sequence Check
        1. 2.2.1.1 Power Supply Ramp with Unstable XI Clock
      2. 2.2.2 Voltage Checks
      3. 2.2.3 Probe the RESET_N Signal
      4. 2.2.4 Probe the RBIAS pin
      5. 2.2.5 Probe the XI Clock
      6. 2.2.6 Probe the Strap Pins During Initialization
      7. 2.2.7 Probe the Serial Management Interface (MDC, MDIO) Signals
        1. 2.2.7.1 Read and Check Register Values
          1. 2.2.7.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Debug the Fiber Connection
      5. 2.3.5 Debug the Start of Frame Detect
      6. 2.3.6 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
      3. 2.4.3 RGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  6. 3Tools and References
    1. 3.1 DP83822 Register Access
    2. 3.2 Software and Driver Debug on Linux
      1. 3.2.1 Common Terminal Outputs and Solutions
  7. 4Summary
  8. 5References
  9. 6Revision History

2.1 Schematic and Layout Checklist

DP83822 Schematic Checklist and DP838XX Layout Checklist are TI files compiling the best practices for designing with DP83822 schematics and layout into a single, simple-to-use document. TI recommends going through this document for more detailed description what connections and components are needed for the PHY to function.

The following sections can present expected behaviors if the PHY is powered and initialized correctly. Any deviations from expected behaviors can point to errors due to incorrect peripheral circuity