SNLA437A December   2023  – October 2025 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826I

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83822 Application Overview
  5. 2Troubleshooting the PHY Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Power Supply Ramp Sequence Check
        1. 2.2.1.1 Power Supply Ramp with Unstable XI Clock
      2. 2.2.2 Voltage Checks
      3. 2.2.3 Probe the RESET_N Signal
      4. 2.2.4 Probe the RBIAS pin
      5. 2.2.5 Probe the XI Clock
      6. 2.2.6 Probe the Strap Pins During Initialization
      7. 2.2.7 Probe the Serial Management Interface (MDC, MDIO) Signals
        1. 2.2.7.1 Read and Check Register Values
          1. 2.2.7.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Debug the Fiber Connection
      5. 2.3.5 Debug the Start of Frame Detect
      6. 2.3.6 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
      3. 2.4.3 RGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  6. 3Tools and References
    1. 3.1 DP83822 Register Access
    2. 3.2 Software and Driver Debug on Linux
      1. 3.2.1 Common Terminal Outputs and Solutions
  7. 4Summary
  8. 5References
  9. 6Revision History

2.5.2 Transmitting and Receiving Packets With the MAC

If generating and checking packets with the MAC is possible, and the PHY has a working link partner with reverse loopback capability, verify the full data path as follows:

  1. Power and connect the PHY to the MAC and a working link partner.
  2. Enable reverse loopback on the link partner.
  3. Transmit test packets from the MAC to the PHY.
  4. Verify the MAC receives the same test packets.

If the MAC receives the same test packets transmitted without issue, the full data path through MAC → PHY → Link Partner (MDI) is valid. If this test does not pass, perform analog loopback to isolate the issue along the data path (disconnect cable side connections before running analog loopback):

  1. Power and connect the PHY to the MAC.
  2. Enable analog loopback on the PHY (write Register 0x0016 = 0x0108).
  3. Transmit test packets from the MAC to the PHY.
  4. Verify the MAC receives the same test packets.

If the MAC receives the same test packets, the data path through MAC → PHY is valid, and the issue has been isolated to the MDI data path. If this test does not pass, the issue can be on the MAC interface. To check the MAC interface, see MII Check.

Below are example sequence of register reads and writes to perform Analog Loopback:

// Analog Loopback

begin

001F 8000 //Hard Reset
0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 0108 //Select Analog Loopback
030B 3380 //This helps PRBS LOCK

0016 3108 //Enables PRBS Checker Config & Packet Generation Enable
 //After you write '3108' the register should Read 3b04. (Bit 11 & 9 go high)
001B 807D //Lock Error Counter's Value
001B

//after running this test check register 0010 bit 0 should be 1 
end