SNLA437A December   2023  – October 2025 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826I

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83822 Application Overview
  5. 2Troubleshooting the PHY Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Power Supply Ramp Sequence Check
        1. 2.2.1.1 Power Supply Ramp with Unstable XI Clock
      2. 2.2.2 Voltage Checks
      3. 2.2.3 Probe the RESET_N Signal
      4. 2.2.4 Probe the RBIAS pin
      5. 2.2.5 Probe the XI Clock
      6. 2.2.6 Probe the Strap Pins During Initialization
      7. 2.2.7 Probe the Serial Management Interface (MDC, MDIO) Signals
        1. 2.2.7.1 Read and Check Register Values
          1. 2.2.7.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Debug the Fiber Connection
      5. 2.3.5 Debug the Start of Frame Detect
      6. 2.3.6 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
      3. 2.4.3 RGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  6. 3Tools and References
    1. 3.1 DP83822 Register Access
    2. 3.2 Software and Driver Debug on Linux
      1. 3.2.1 Common Terminal Outputs and Solutions
  7. 4Summary
  8. 5References
  9. 6Revision History

2.3.4 Debug the Fiber Connection

Fiber Network Circuit shows the recommended circuit for a 100-Mbps fiber network. Verify that the circuit meets the requirements of the intended application.

All resistors and capacitors should be placed as close to the fiber transceiver as possible.

Fiber Network CircuitFigure 2-12 Fiber Network Circuit
Note: For PECL and LVPECL applications and for the recommended additional capacitors and resistors needed, see DP83822 EVM User's Guide.
Note: SFP Fiber Transceiver usually have integrated AC coupling capacitors. Adding external capacitors may not be needed.

The DP83822 provides IEEE 802.3 compliant 100BASE-FX operation. Hardware bootstrap or register configuration can be used to enable 100BASE-FX operation.

The DP83822IF and DP83822HF are the fiber capable variants of the DP83822. Register 0x0001[2] indicates link status for both Copper and Fiber modes of operation. In Fiber, this bit does NOT toggle when the link status changes. Soft-Reset must be performed (Set Register 0x001F = 0x4000) before reading Register 0x0001 to ensure proper link status change update.

The DP83822 has signal detection pin. This pin connects to an industry standard fiber transceiver. When enabling 100BASE-FX operation using the FX_EN bootstrap, AMDIX_EN bootstrap turns into SD_EN bootstrap. Please refer to Table 2-12 for fiber bootstrap configuration.

Note: 100BASE-FX signal detect pin (LED_1) polarity is controlled by bit[0] in the Fiber General Configuration Register (FIBER GENCFG, Register 0x0465). Please refer to Table 2-13. By default, signal detect is an active HIGH polarity.
Note: TI recommends connecting Signal Detect pin from the Optical Transceiver to the LED_1 pin and enable it using SD_EN bootstrap pin in 100BASE-FX mode. The LED_1 pin is not used in design and that, if the electrical link between the fiber module and the DP83822 is broken, disconnected or otherwise disrupted, the link will recover only by initiating a soft reset through MDIO/MDC interface.
Table 2-12 Fiber Bootstrap Configuration
Pin NamePin#PU/PDModeDescription
COL29PU2 or 3FX_EN: Enables 100BASE-FX
RX_ER28PU3 or 4SD_EN: Enables active HIGH 100BASE-FX Signal Detection on LED_1 when set to '1' if FX_EN is enabled. Polarity can be changed using the Fiber General Configuration Register (FIBER GENCFG, Register 0x0465).
Table 2-13 0x0465 Fiber General Configuration Register (FIBER GENCFG)
BitNameTypeDefaultFunction
0100Base-FX Signal Detect PolarityR/W0100Base-FX Signal Detect Polarity: 1 = Signal Detect is Active LOW 0 = Signal Detect is Active HIGH When set to Active HIGH, Link drop will occur if SD pin senses a LOW state (SD = '0'). When set to Active LOW, Link drop will occur if SD pin senses a HIGH state (SD = '1'). Note: To enable 100BaseFX Signal Detection on LED_1 (pin #24), strap SD_EN = '1'