SNLA437A December   2023  – October 2025 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83826I

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83822 Application Overview
  5. 2Troubleshooting the PHY Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Power Supply Ramp Sequence Check
        1. 2.2.1.1 Power Supply Ramp with Unstable XI Clock
      2. 2.2.2 Voltage Checks
      3. 2.2.3 Probe the RESET_N Signal
      4. 2.2.4 Probe the RBIAS pin
      5. 2.2.5 Probe the XI Clock
      6. 2.2.6 Probe the Strap Pins During Initialization
      7. 2.2.7 Probe the Serial Management Interface (MDC, MDIO) Signals
        1. 2.2.7.1 Read and Check Register Values
          1. 2.2.7.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Debug the Fiber Connection
      5. 2.3.5 Debug the Start of Frame Detect
      6. 2.3.6 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
      3. 2.4.3 RGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  6. 3Tools and References
    1. 3.1 DP83822 Register Access
    2. 3.2 Software and Driver Debug on Linux
      1. 3.2.1 Common Terminal Outputs and Solutions
  7. 4Summary
  8. 5References
  9. 6Revision History

2.2.1 Power Supply Ramp Sequence Check

Ensure the device is being powered according to the recommended power supply ramp sequence. Power up the device and probe the voltage rails of the PHY to ensure that the voltages are within limits defined in Table 2-24. Verify that the power up voltage parameter timings are within the limits defined in Table 2-2 and Figure 2-1.

Table 2-1 PHY Supply Voltage Specifications
DescriptionsMinTypMaxUnit
VDDIOSupply Voltage 1/O = 1.8V1.711.81.89V
Supply Voltage I/O = 2.5V2.3752.52.625
Supply Voltage I/O = 3.3V3.153.33.45
AVDSupply Voltage Analog = 3.3V3.153.33.45V
Supply Voltage Analog = 1.8V1.711.81.89
Center Tap (CT)Supply Voltage Center Tap = 3.3V3.153.33.45V
Supply Voltage Center Tap = 1.8V1.711.81.89
Table 2-2 Timing Requirements: Power-Up Timing
ParameterTest ConditionsMINTYPMAXUnit
T1AVD (analog supply) ramp delay post VDDIO (digital supply) ramp.
AVD and VDDIO potential must not exceed 0.3V prior to supply ramp.		Time from start of supply ramp–100100ms
VDDIO ramp time100ms
AVD ramp time100ms
T2Post power-up stabilization time prior to MDC preamble for register accesses.
MDC preamble coming in any time after this max wait time will be valid.		MDIO is pulled high for 32-bit serial management initialization200ms
T3Hardware configuration latch-in time for power up200ms
T4Hardware configuration pins transition to output drivers64ns
T5Fast Link Pulse transmission delay post power up1.5s
Power-Up TimingFigure 2-1 Power-Up Timing
Note: If a link up issue is present for DP83822 and the AVD is operated in 3.3V, check register 0x0421 to see AVD level and VDDIO level match the desire output. Register 0x0421 bit[2]=1 for 3.3V AVD. Register 0x0x421 bit[1:0]=11 for 3.3V VDDIO If register 0x0421 does not match with the desire result, write 0x041F register to the desire voltage level. Write register 0x041F bit[12] = 1 for 3.3V AVD and bit[11:10]=11 for 3.3V VDDIO. Registers 0x0421 and 0x041F are extended registers, make sure to follow Extended Register Access.