SNLA473 November   2024 DP83867CS , DP83867E , DP83867IS , DP83869HM , DP83TC811S-Q1 , DP83TC812S-Q1 , DP83TC813S-Q1 , DP83TC814S-Q1 , DP83TC817S-Q1 , DP83TC818S-Q1 , DP83TG720S-Q1 , DP83TG721S-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Troubleshooting the MAC Interface - SGMII
    1. 1.1 Verify Bootstrap Configurations
      1. 1.1.1 SGMII Bootstrap Configuration for DP83TG720S-Q1
    2. 1.2 Read and Check Register Values
    3. 1.3 Auto-Negotiation
    4. 1.4 Throughput and Loopback Testing
      1. 1.4.1 Bidirectional Throughput Testing
      2. 1.4.2 RX and TX Throughput Testing
      3. 1.4.3 RX and TX Throughput Testing with Fixed Number of Packets
      4. 1.4.4 Loopback Testing
        1. 1.4.4.1 MII Loopback
        2. 1.4.4.2 Reverse Loopback
    5. 1.5 Check the Clock Signal
    6. 1.6 Measure the SGMII Eye
      1. 1.6.1 SGMII Eye Mask Requirements
    7. 1.7 SGMII Layout
  5. 2Summary
  6. 3References

1.2 Read and Check Register Values

Read the registers and verify that SGMII link is up and SGMII auto negotiation is completed. Note that the initial values of some registers can vary based on strap options.

Shown below are examples of register dumps for the DP83TG720-Q1 and the DP83869. These are possible values for when MDI link is up, the PHY is in SGMII mode, and SGMII link is up.

Table 1-3 DP83TG720S-Q1 Automotive PHY - SGMII Register Values
Register Address Register Name Example Value Description
0x0000 BMCR 0x0140 Bit[14] can be used to configure MII loopback.
0x0001 BMSR 0x0145 Bit[2] indicates MDI link is up.
0x0011 MII_REG_11 0x000B Bit[11] can be asserted to initiate SGMII soft reset.
0x0428 A2D_REG_40 0x6002 Bits [14:13] indicate output voltage swing is 720mV. Bits can be toggled to increase SGMII output swing.
0x045D SOR_VECTOR_1 0x0000 Bit[13] indicates SGMII is enabled, Bits [8:6] indicate MAC mode the PHY has been strapped into.
0x0608 SGMII_CTRL_1 0x027B Bit[0] indicates SGMII auto-negotiation is enabled, Bits [2:1] indicate auto-negotiation timer is 2us. These bits can be toggled to adjust timer.
0x060A SGMII_STATUS 0x0d46 Bit[11] indicates SGMII link is up, Bit[10] indicates SGMII auto-negotiation is complete.
0x060C SGMII_CTRL_2 0x001B Bit[6] can be asserted to restart SGMII auto-negotiation when there is no SGMII link. Bits [5:3] indicate TX and Bits [2:0] indicate RX fifo half full threshold.
0x060D SGMII_FIFO_STATUS 0x0000 Bit[0] indicates packet underflow. Bit[1] indicates packet overflow.
0x0639 PKT_STAT_1 0x0000 Register value indicates TX packet counter.
0x063A PKT_STAT_2 0x0000 Register value indicates TX packet counter.
0x063B PKT_STAT_3 0x0000 TX packet error counter.
0x063C PKT_STAT_4 0x0000 Register value indicates RX packet counter.
0x063D PKT_STAT_5 0x0000 Register value indicates RX packet counter.
0x063E PKT_STAT_6

0x0000

 RX packet error counter.
Note: Registers 0x0639, 0x063A, 0x063B are cleared when read in sequence. Similarly, registers 0x063C, 0x063D, 0x063E are also cleared when read in sequence.
Table 1-4 DP83869HM Industrial PHY - SGMII Register Values
Register Address Register Name Example Value Description
0x0000 BMCR 0x1140 Bit[14] can be used to configure MII loopback.
0x0001 BMSR 0x796D Bit[2] indicates MDI link is up
0x0014 GEN_CFG2 0x29C7 Bit[7] enables SGMII auto-negotiation.
0x0031 GEN_CFG3 0x10B0 Bits [6:5] can be toggled to adjust auto-negotiation timer.
0x0037 SGMII_AUTO_NEG_STATUS 0x0001 Bit[0] indicates SGMII auto-negotiation is complete.