SNLA492 September   2025 TDP2004-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Access Methods
    1. 2.1 Pin-Strap Mode
    2. 2.2 SMBus, I2C Primary Mode
    3. 2.3 SMBus, I2C Secondary Mode
  6. 3Register Mapping
    1. 3.1 Shared Registers
    2. 3.2 Channel Registers
  7. 4RX Equalization Control Settings
  8. 5Flat-Gain
  9. 6RX Equalization and Flat Gain Selection Matrix
  10. 7TDP2004-Q1 Programming Example
    1. 7.1 PD Control Through Register Programming
    2. 7.2 Broadcast Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
    3. 7.3 Individual Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
  11. 8Summary
  12. 9References

2 Access Methods

For the TDP2004-Q1, there are five 5-level input pins:

  • MODE
  • EQ0/ADDR0
  • EQ1/ADDR1
  • GAIN/SDA
  • TEST/SCL.

These 5-level inputs use an external resistor to help set the five valid levels as shown in Table 2-1.

Table 2-1 TDP2004-Q1 5-Level Control Pin Settings
LevelSetting
L01kΩ to GND
L18.25kΩ to GND
L224.9kΩ to GND
L375kΩ to GND
L4Floating

The TDP2004-Q1 can be configured in three different ways through the MODE pin:

Table 2-2 TDP2004-Q1 Mode Configuration
Level Configuration
L0 Pin-strap mode
L1 SMBus/ I2C primary mode
L2 SMBus/ I2C secondary mode
L3 and L4 Reserved

Pin strap mode – The TDP2004-Q1 control configuration is done solely by strap pins.

SMBus/I2C Primary mode – The TDP2004-Q1 control configuration is automatically read from an external EEPROM.

SMBus/I2C Secondary mode – The TDP2004-Q1 control configuration is controlled through an external Serial Management Bus (SMBus/I2C)