SNLU317A september   2022  – may 2023 DP83867E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
    2. 1.2 Hardware Features
    3. 1.3 Software Features
    4. 1.4 Block Diagram
  5. 2Board Overview
    1. 2.1 Components
    2. 2.2 PCIe Header Signals
      1. 2.2.1 MISC0 Signal Header
      2. 2.2.2 MISC1 Signal Header
      3. 2.2.3 RGMII Signal Header
  6. 3Quick Start
  7. 4Schematic, Board Layout, and Bill of Materials
    1. 4.1 Board Layout
    2. 4.2 Schematic
    3. 4.3 Bill of Materials
  8. 5Revision History

2.2.3 RGMII Signal Header

RGMII signal header for PHY1 can be used to connect PHY1 via separate cable connection.

Table 2-4 RGMII Signal Header for PHY1

Pin Number

Signal Description

1

TXCLK

2

RXCLK

3

TXCTL

4

RXCTL

7

TXDATA_3

8

RXDATA_3

9

TXDATA_2

10

 RXDATA_2

11

 TXDATA_1

12

 RXDATA_1

13

 TXDATA_0

14

 RXDATA_0

5, 6, 15, 16

GND