SNLU317A september   2022  – may 2023 DP83867E

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
    2. 1.2 Hardware Features
    3. 1.3 Software Features
    4. 1.4 Block Diagram
  5. 2Board Overview
    1. 2.1 Components
    2. 2.2 PCIe Header Signals
      1. 2.2.1 MISC0 Signal Header
      2. 2.2.2 MISC1 Signal Header
      3. 2.2.3 RGMII Signal Header
  6. 3Quick Start
  7. 4Schematic, Board Layout, and Bill of Materials
    1. 4.1 Board Layout
    2. 4.2 Schematic
    3. 4.3 Bill of Materials
  8. 5Revision History

2.2.2 MISC1 Signal Header

The MSIC1 signal header is for debug purposes.

Table 2-3 MISC1 Signal Header for PHY2
Pin Number Signal Description
1 MDC PHY2
3 MDIO PHY2
5 Interrupt PHY2
7 AUXTS PHY2 (Start-of-Frame time stamp)
9 PPS PHY2 (not supported by AIC)
11 Reset PHY2
13, 15 Not connected
2, 4, 6, 8, 10, 12, 14, 16 GND