SNOSAS1B November   2010  – September 2025 LMD18200QML

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Diagram
  6. 5 Absolute Maximum Ratings
  7. 6 Operating Ratings
  8. 7 Quality Conformance Inspection
  9. 8 LMD18200 Electrical Characteristics DC Parameters
  10. 9 Typical Performance Characteristics
  11. 10Test Circuit
    1. 10.1 Switching Time Definitions
  12. 11Pinout Description
    1. 11.1 Application Information
      1. 11.1.1 TYPES OF PWM SIGNALS
      2. 11.1.2 SIGNAL TRANSITION REQUIREMENTS
      3. 11.1.3 USING THE CURRENT SENSE OUTPUT
      4. 11.1.4 USING THE THERMAL WARNING FLAG
      5. 11.1.5 SUPPLY BYPASSING
      6. 11.1.6 CURRENT LIMITING
      7. 11.1.7 INTERNAL CHARGE PUMP AND USE OF BOOTSTRAP CAPACITORS
      8. 11.1.8 INTERNAL PROTECTION DIODES
    2. 11.2 Typical Applications
      1. 11.2.1 FIXED OFF-TIME CONTROL
      2. 11.2.2 TORQUE REGULATION
      3. 11.2.3 VELOCITY REGULATION
  13. 12Revision History

11.1.2 SIGNAL TRANSITION REQUIREMENTS

To ensure proper internal logic performance, it is good practice to avoid aligning the falling and rising edges of input signals. A delay of at least 1 µsec should be incorporated between transitions of the Direction, Brake, and/or PWM input signals. A conservative approach is be sure there is at least 500ns delay between the end of the first transition and the beginning of the second transition. See Figure 11-3.

LMD18200QML Transitions in Brake, Direction, or PWM Must Be Separated By At Least 1 µsecFigure 11-3 Transitions in Brake, Direction, or PWM Must Be Separated By At Least 1 µsec