SNOSDL5 January   2025 LMG2652

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 GaN Power FET Switching Capability
      2. 7.3.2 Current-Sense Emulation
      3. 7.3.3 Bootstrap Diode Function
      4. 7.3.4 Input Control Pins (EN, INL, INH, GDH)
      5. 7.3.5 INL - INH Interlock
      6. 7.3.6 AUX Supply Pin
        1. 7.3.6.1 AUX Power-On Reset
        2. 7.3.6.2 AUX Under-Voltage Lockout (UVLO)
      7. 7.3.7 BST Supply Pin
        1. 7.3.7.1 BST Power-On Reset
        2. 7.3.7.2 BST Under-Voltage Lockout (UVLO)
      8. 7.3.8 Overcurrent Protection
      9. 7.3.9 Overtemperature Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 LLC Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 AHB Application
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.3 Recommended Operating Conditions

Unless otherwise noted: voltages are respect to AGND
MIN NOM MAX UNIT
Supply voltage AUX 10 26 V
Supply voltage to SW BST 7.5 26 V
Input voltage EN, INL, INH 0 VAUX V
Input voltage to SW GDH 0 VBST_SW V
VIH High-level input voltage EN, INL, INH, GDH to SW 2.5 V
VIL Low-level input voltage 0.6 V
ID(cnts)(ls) Low-side drain (SW to SL) continuous current, FET on –6.1 6.1 A
ID(cnts)(hs) High-side drain (DH to SW) continuous current, FET on –6.1 6.1 A
CAUX AUX to AGND capacitance from external bypass capacitor 3 x CBST µF
CBST_SW BST to SW capacitance from external bypass capacitor 0.010 µF