SNOSDM7 August   2025 OPA4H838-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: VS = ±1.25V to ±2.75V (VS = 2.5 to 5.5V)
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Voltage
      2. 6.3.2 Input Voltage and Zero-Crossover Functionality
      3. 6.3.3 Input Differential Voltage
      4. 6.3.4 Internal Offset Correction
      5. 6.3.5 EMI Susceptibility and Input Filtering
    4. 6.4 Device Functional Modes
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Bidirectional Current-Sensing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Single Operational Amplifier Bridge Amplifier
      3. 7.2.3 Precision, Low-Noise, DAC Buffer
      4. 7.2.4 Load Cell Measurement
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI™ Simulation Software (Free Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

OPA4H838-SEP OPA4H838-SEP PW Package, 14-Pin TSSOP-14 (Top View)Figure 4-1 OPA4H838-SEP PW Package, 14-Pin TSSOP-14 (Top View)

 

Pin Functions: OPA4H838-SEP
PIN I/O DESCRIPTION
NAME PW (TSSOP)
–IN A 2 I Inverting input, channel A
–IN B 6 I Inverting input, channel B
–IN C 9 I Inverting input, channel C
–IN D 13 I Inverting input, channel D
+IN A 3 I Noninverting input, channel A
+IN B 5 I Noninverting input, channel B
+IN C 10 I Noninverting input, channel C
+IN D 12 I Noninverting input, channel D
OUT A 1 O Output, channel A
OUT B 7 O Output, channel B
OUT C 8 O Output, channel C
OUT D 14 O Output, channel D
V– 11 — Negative (lowest) power supply
V+ 4 — Positive (highest) power supply