SNVSA21H May   2014  – April 2025 LP8860-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
    1.     Pin Functions
  7. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Current Sinks Electrical Characteristics
    7. 5.7  Boost Converter Characteristics
    8. 5.8  Logic Interface Characteristics
    9. 5.9  VIN Undervoltage Protection (VIN_UVLO)
    10. 5.10 VDD Undervoltage Protection (VDD_UVLO)
    11. 5.11 VIN Overvoltage Protection (VIN_OVP)
    12. 5.12 VIN Overcurrent Protection (VIN_OCP)
    13. 5.13 Power-Line FET Control Electrical Characteristics
    14. 5.14 External Temp Sensor Control Electrical Characteristics
    15. 5.15 I2C Serial Bus Timing Parameters (SDA, SCLK)
    16. 5.16 SPI Timing Requirements
    17. 5.17 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Boost Controller
      2. 6.1.2 LED Output Configurations
      3. 6.1.3 Display Mode
      4. 6.1.4 Cluster Mode
      5. 6.1.5 Hybrid Dimming
      6. 6.1.6 Charge Pump and Square Waveform (SQW) Output
      7. 6.1.7 Power-Line FET
      8. 6.1.8 Protection Features
      9. 6.1.9 Advanced Thermal Protection Features
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Clock Generation
        1. 6.3.1.1 LED PWM Clock Generation With VSYNC
        2. 6.3.1.2 LED PWM Frequency and Resolution
      2. 6.3.2 Brightness Control (Display Mode)
        1. 6.3.2.1 PWM Input Duty Cycle Based Control
        2. 6.3.2.2 Brightness Register Control
        3. 6.3.2.3 PWM Input Duty × Brightness Register
        4. 6.3.2.4 PWM-Input Direct Control
        5. 6.3.2.5 Brightness Slope
        6. 6.3.2.6 LED Dimming Methods
        7. 6.3.2.7 PWM Calculation Data Flow for Display Mode
      3. 6.3.3 LED Output Modes and Phase Shift PWM (PSPWM) Scheme
      4. 6.3.4 LED Current Setting
      5. 6.3.5 Cluster Mode
      6. 6.3.6 Boost Controller
      7. 6.3.7 Charge Pump
      8. 6.3.8 Powerline Control FET
      9. 6.3.9 Protection and Fault Detection Modes
        1. 6.3.9.1 LED Fault Comparators and Adaptive Boost Control
        2. 6.3.9.2 LED Current Dimming With Internal Temperature Sensor
        3. 6.3.9.3 LED Current Limitation With External NTC Sensor
        4. 6.3.9.4 LED Current Dimming With External NTC Sensor
        5. 6.3.9.5 Protection Feature and Fault Summary
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby Mode
      2. 6.4.2 Active Mode
      3. 6.4.3 Fault Recovery State
      4. 6.4.4 Start-Up and Shutdown Sequences
    5. 6.5 Programming
      1. 6.5.1 EEPROM
      2. 6.5.2 Serial Interface
        1. 6.5.2.1 SPI Interface
        2. 6.5.2.2 I2C Serial Bus Interface
          1. 6.5.2.2.1 Interface Bus Overview
          2. 6.5.2.2.2 Data Transactions
          3. 6.5.2.2.3 Acknowledge Cycle
          4. 6.5.2.2.4 Acknowledge After Every Byte Rule
          5. 6.5.2.2.5 Addressing Transfer Formats
          6. 6.5.2.2.6 Control Register Write Cycle
          7. 6.5.2.2.7 Control Register Read Cycle
    6. 6.6 Register Maps
      1. 6.6.1 Register Bit Explanations
        1. 6.6.1.1  Display/Cluster1 Brightness Control MSB
        2. 6.6.1.2  Display/Cluster1 Brightness Control LSB
        3. 6.6.1.3  Display/Cluster1 Output Current MSB
        4. 6.6.1.4  Display/Cluster1 Output Current LSB
        5. 6.6.1.5  Cluster2 Brightness Control MSB
        6. 6.6.1.6  Cluster2 Brightness Control LSB
        7. 6.6.1.7  Cluster2 Output Current
        8. 6.6.1.8  Cluster3 Brightness Control MSB
        9. 6.6.1.9  Cluster3 Brightness Control LSB
        10. 6.6.1.10 Cluster3 Output Current
        11. 6.6.1.11 Cluster4 Brightness Control MSB
        12. 6.6.1.12 Cluster4 Brightness Control LSB
        13. 6.6.1.13 Cluster4 Output Current
        14. 6.6.1.14 Configuration
        15. 6.6.1.15 Status
        16. 6.6.1.16 Fault
        17. 6.6.1.17 LED Fault
        18. 6.6.1.18 Fault Clear
        19. 6.6.1.19 Identification
        20. 6.6.1.20 Temp MSB
        21. 6.6.1.21 Temp LSB
        22. 6.6.1.22 Display LED Current MSB
        23. 6.6.1.23 Display LED Current LSB
        24. 6.6.1.24 Display LED PWM MSB
        25. 6.6.1.25 Display LED PWM LSB
        26. 6.6.1.26 EEPROM Control
        27. 6.6.1.27 EEPROM Unlock Code
      2. 6.6.2 EEPROM Bit Explanations
        1. 6.6.2.1  EEPROM Register 0
        2. 6.6.2.2  EEPROM Register 1
        3. 6.6.2.3  EEPROM Register 2
        4. 6.6.2.4  EEPROM Register 3
        5. 6.6.2.5  EEPROM Register 4
        6. 6.6.2.6  EEPROM Register 5
        7. 6.6.2.7  EEPROM Register 6
        8. 6.6.2.8  EEPROM Register 7
        9. 6.6.2.9  EEPROM Register 8
        10. 6.6.2.10 EEPROM Register 9
        11. 6.6.2.11 EEPROM Register 10
        12. 6.6.2.12 EEPROM Register 11
        13. 6.6.2.13 EEPROM Register 12
        14. 6.6.2.14 EEPROM Register 13
        15. 6.6.2.15 EEPROM Register 14
        16. 6.6.2.16 EEPROM Register 15
        17. 6.6.2.17 EEPROM Register 16
        18. 6.6.2.18 EEPROM Register 17
        19. 6.6.2.19 EEPROM Register 18
        20. 6.6.2.20 EEPROM Register 19
        21. 6.6.2.21 EEPROM Register 20
        22. 6.6.2.22 EEPROM Register 21
        23. 6.6.2.23 EEPROM Register 22
        24. 6.6.2.24 EEPROM Register 23
        25. 6.6.2.25 EEPROM Register 24
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Application for Display Backlight
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Inductor Selection
          2. 7.2.1.2.2  Output Capacitor Selection
          3. 7.2.1.2.3  Input Capacitor Selection
          4. 7.2.1.2.4  Charge Pump Output Capacitor
          5. 7.2.1.2.5  Charge Pump Flying Capacitor
          6. 7.2.1.2.6  Diode
          7. 7.2.1.2.7  Boost Converter Transistor
          8. 7.2.1.2.8  Boost Sense Resistor
          9. 7.2.1.2.9  Power Line Transistor
          10. 7.2.1.2.10 Input Current Sense Resistor
          11. 7.2.1.2.11 Filter Component Values
            1. 7.2.1.2.11.1 Critical Components for Design
        3. 7.2.1.3 Application Performance Plots
      2. 7.2.2 Low VDD Voltage and Combined Output Mode Application
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Performance Plots
      3. 7.2.3 High Output Voltage Application
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Performance Plots
      4. 7.2.4 High Output Current Application
        1. 7.2.4.1 Design Requirements
        2. 7.2.4.2 Detailed Design Procedure
        3. 7.2.4.3 Application Performance Plots
      5. 7.2.5 Three-Channel Configuration Without Serial Interface
        1. 7.2.5.1 Design Requirements
        2. 7.2.5.2 Detailed Design Procedure
        3. 7.2.5.3 Application Performance Plots
      6. 7.2.6 Solution With Minimum External Components
        1. 7.2.6.1 Design Requirements
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

6.3.9.5 Protection Feature and Fault Summary

Table 6-17 summarizes protection features and related faults.

Table 6-17 Overview of the Fault/Protection Schemes
FAULT/PROTECTIONFAULT NAMETHRESHOLDACTION(1)(2)MASK(4)FAULT CLEARING(3)(5)
Input overvoltage protectionVIN_OVPOVP_LEVEL[1:0] (V)VIN overvoltage monitored from soft start. Fault causes entry to FAULT_RECOVERY state. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared.
FAULT pin is pulled low.		MASK_OVP_FSM
Masks fault recovery, but not status and fault pin operations		Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
00OFF
017
1011
1122.5
Input undervoltage protectionVIN_UVLOUVLO_LEVEL[1:0] (V)VIN undervoltage monitored from soft start. Fault causes entry to FAULT_RECOVERY state. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared.
FAULT pin is pulled low.		MASK_VIN_UVLO
Masks fault recovery, status and fault pin operations		Fault bit and FAULT pin:
1.POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
00OFF
013
105
118
VDD undervoltage protectionVDD_UVLOVDD_UVLO_LEVEL
Threshold (V)		Device enters STANDBY state. Recovers when fault disappears. All registers are cleared or reloaded from EEPROM (if defined) with exception registers 0x00, 0x01, 0x04…0x0C. After recovery LP8860-Q1 provides the same brightness as before fault detection, if DISP_CL1_CURRENT[11:0] context stays same as LED_CURRENT_CTRL[11:0] EEPROM setting. If VDD voltage goes below POR level, registers 0x00, 0x01, 0x04…0x0C are cleared.
This fault does not have any flags and doesn’t generate FAULT. Voltage hysteresis is 50 mV (typical).
02.5
13
Boost overcurrent protectionBOOST_OCPVBOOST longer than 110 ms 5 V (typical) below set value.
Set value is voltage value defined by logic during adaptation in adaptive mode or initial boost voltage setting in manual mode.		Fault monitoring started from boost start. Fault causes entry to FAULT_RECOVERY state. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared.
FAULT pin is pulled low.		MASK_BOOST_OCP_ FSM
Masks fault recovery, but not status and fault pin operations		Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
Boost overvoltage protectionBOOST_OVPVBOOST voltage 1.6 V (typical) above set value
Set value is voltage value defined by logic during adaptation in adaptive mode or initial boost voltage setting in manual mode.		Boost OVP fault monitored during normal operation
FAULT pin is pulled low.		MASK_BOOST_OVP_ STATUSFault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
Input voltage overcurrent protectionPL_FET_FAULTPL_SD_LEVEL[1:0] (A)Fault is detected with 2 methods:
1. Detects overcurrent from soft start by measuring RISENSE voltage.
2. Detects FB voltage at the end of soft start. If voltage is below 1.2 V, fault is detected. Fault causes entry to FAULT_RECOVERY state. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared.
FAULT pin is pulled low.		Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
106
118
Short LED faultSHORT_LEDDRV_LED_FAULT_THR[1:0] (V)LED output in display mode: Triggered if one or more outputs voltage is above DRV_LED_FAULT_THR and at least one LED output voltage is between DRV_HEADR and DRV_HEADR + DRV_LED_COMP_HYST. Is set only if LED faults are enabled in EEPROM. Shorted string is removed from voltage control loop and LED current sink n is disabled.
LED output in cluster mode: If one or more outputs voltage above DRV_LED_FAULT_THR fault is detected. Is pulled low only if LED faults are enabled in EEPROM. Shorted string PWM output is disabled.
FAULT pin is pulled low.		EN_DISPLAY_LED_ FAULT for LEDs in display mode EN_CL_LED_FAULT for LEDs in cluster modeFault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
When fault is cleared it can be set again only during next POR or if there is another LED short fault in different output.
003.6
013.6
106.9
1110.6
DRV_LED_COMP_HYST[1:0] (mV)
001000
01750
10500
11250
Open LED faultOPEN_LEDDRV_HEADR[2:0] (mV)LED output in display mode: Triggered if one or more outputs voltage is below DRV_HEADR, and boost adaptive control has reach the maximum voltage. Is set only if led faults enabled in EEPROM. Open string is removed from voltage control loop and PWM generation is disabled.
LED output in cluster mode: Triggered if one or more outputs voltage is below DRV_HEADR. Is set only if LED faults enabled in EEPROM. Open string PWM generation is disabled.
FAULT pin is pulled low.		EN_DISPLAY_LED
_FAULT
for LEDs in display mode
EN_CL_LED_FAULT
for LEDs in cluster mode		Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
When open fault is cleared it can set again only during next power-up or if there is another LED open fault.
111VSAT+50
110VSAT+175
101VSAT+300
100VSAT+450
011VSAT+575
010VSAT+700
001VSAT+875
000VSAT+1000
LED faultsLED_FAULT[4:1]Defines which string has either open or short fault. Cleared only during power down.POR or VDDIO/EN
Charge pump faultCP_2X_ FAULTVCPUMD < 0.85 × (2 × VDD) (typical)Charge pump voltage not high enough condition. Fault causes entry to FAULT_RECOVERY state. CP voltage monitored from the boost soft start. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared.
FAULT pin is pulled low.		Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
Thermal Current Limit (LED Outputs)No faultsINT_TEMP_LIM[1:0]When die temperature increases temperature defined by INT_TEMP_LIM[1:0] the device automatically lowers the PWM duty for outputs 2.25%/°C (typical). For Hybrid PWM and Current dimming mode current is used for brightness reduction as well.
00
01
10
11		disabled
90°C
100°C
110°C
Thermal LED Current Limit with external NTC sensor.EXT_TEMP_ FLAG_LEXT_TEMP_LEVEL_LOW[3:0]Fault is monitored during normal operation. If EXT_TEMP_LEVEL_LOW[3:0] is exceeded, LED current is reduced.
FAULT pin is pulled low when EXT_TEMP_FLAG_L goes high.		EXT_TEMP_COMP_EN=0 disables faultFault bit:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin when fault deasserted.
Fault pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
SettingLevel (kΩ)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111		79.67
43.35
29.77
22.67
18.30
15.34
13.21
11.60
10.34
9.32
8.49
7.79
7.20
6.69
6.25
5.87
EXT_TEMP_ FLAG_HEXT_TEMP_LEVEL_HIGH[3:0]Fault is monitored during normal operation. If EXT_TEMP_LEVEL_HIGH[3:0] limit is exceeded, the LED outputs are turned off.
FAULT pin is pulled low.		EXT_TEMP_COMP_EN=0 disables faultFault bit:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin when fault deasserted.
Fault pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
SettingLevel (kΩ)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111		79.67
43.35
29.77
22.67
18.30
15.34
13.21
11.60
10.34
9.32
8.49
7.79
7.20
6.69
6.25
5.87
NTC missingTEMP_RES_ MISSINGResistance > 2 MΩNTC is missing. Fault is monitored during normal operation. Not connected to FAULT output pin. TEMP_RES_FAULT is monitored if EXT_TEMP_COMP_EN EEPROM bit has been enabledEXT_TEMP_COMP_EN=0 disables fault1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
Thermal shutdownTSDRising temperature =165°C
Falling temperature = 135°C		Thermal shutdown is monitored from soft start. Fault causes entry to the FAULT_RECOVERY state.
FAULT pin is pulled low.		Fault bit and FAULT pin:
1. POR or VDDIO/EN
2. Writing CLEAR_FAULTS bit or toggling NSS pin
(1) Recovery time is 100 ms.
(2) During fault recovery state the LED outputs and boost is shut down and power-line FET is turned off.
(3) If fault is cleared during fault recovery state, FAULT pin is pulled low again after recovery state, if this fault still exists.
(4) If fault recovery is masked, fault bit sets again after cleaning.
(5) The NSS pin can be used for fault reset only for I2C interface mode. NSS is level sensitive; be aware NSS is set to low after fault reset.

Fault detection is digitally filtered — filtering time for different faults is shown in Table 6-18.

Table 6-18 Fault Filters
FAULT/PROTECTONFAULT NAMETIMEENABLED
Boost Overcurrent ProtectionBOOST_OCP110 msFrom boost start
Boost Overvoltage ProtectionBOOST_OVP100 µsIn normal mode
Input Overvoltage ProtectionVIN_OVP100 µsFrom soft start
Input Undervoltage ProtectionVIN_UVLO100 µsFrom soft start
Input Overcurrent ProtectionPL_FET_FAULT100 µsFrom soft start
VDD Undervoltage ProtectionVDD_UVLO5 µsAlways
Thermal ShutdownTSD100 µsFrom soft start
Charge Pump faultCP_2X_FAULT10 µsFrom boost start
Thermal LED Current Limit with external NTC sensor.EXT_TEMP_FLAG_H10 µsIn normal mode
EXT_TEMP_FLAG_L10 µsIn normal mode
NTC missingTEMP_RES_FAULT100 µsIn normal mode
LP8860-Q1 Input OVP Triggering and RecoveryFigure 6-29 Input OVP Triggering and Recovery
LP8860-Q1 Input OVP Triggering and RecoveryFigure 6-31 Input OVP Triggering and Recovery
LP8860-Q1 Boost OVP Triggering and RecoveryFigure 6-33 Boost OVP Triggering and Recovery
LP8860-Q1 Input UVLO Triggering and RecoveryFigure 6-30 Input UVLO Triggering and Recovery
LP8860-Q1 Boost OCP Triggering and RecoveryFigure 6-32 Boost OCP Triggering and Recovery