SNVSB66A July 2018 – October 2021 TPS3431
The watchdog is often needed to be disabled during startup to allow for an initialization period. When the initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by the TPS3431. To achieve this setup, EN on TPS3431 is controlled by TPS3890 supervisor. In this application, the TPS3890 was chosen to monitor VDD as well, which means that the RESET on the TPS3890 stays low until VDD rises above VITN. When VDD comes up, the delay time can be adjusted through the CT capacitor on the TPS3890. With this approach, the RESET delay can be adjusted from a minimum of 25 μs to a maximum of 30 seconds. For this design, a typical delay of 5 seconds is needed before the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890 data sheet) yields an ideal capacitance of 4.67 μF, giving a closest standard ceramic capacitor value of 4.7 μF. When connecting a 4.7 μF capacitor from CT to GND, the typical delay time is 5 seconds. Figure 8-7 shows that when the watchdog is disabled, the WDO output remains high. However when SET1 goes high and there is no WDI signal, WDO begins to assert. See the TPS3890 datasheet for detailed information on the TPS3890. The ENOUT pin on the TPS3431 reflects the status of the EN pin and can be connected to the microcontroller for monitoring or can be left floating if not being used. When the TPS3431 is disabled, ENOUT is logic low and WDO is logic high so the user can also tie ENOUT to WDO to force WDO to logic low when TPS3431 is disabled.