SNVSCN2A September   2024  – September 2025 TPS37100-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 7.3.1.2 Power-On Reset (VDD < VPOR )
      2. 7.3.2 SENSE
        1. 7.3.2.1 Adjustable Voltage Thresholds
        2. 7.3.2.2 SENSE Hysteresis
        3. 7.3.2.3 Reverse Polarity Protection
      3. 7.3.3 Output Logic Configurations
        1. 7.3.3.1 Open-Drain
        2. 7.3.3.2 Active-Low (OUT A and OUT B)
      4. 7.3.4 User-Programmable Release Time Delay
        1. 7.3.4.1 Deassertion Time Delay Configuration
      5. 7.3.5 User-Programmable Sense Delay
        1. 7.3.5.1 Sense Time Delay Configuration
      6. 7.3.6 Analog Out
      7. 7.3.7 Built-in Self-Test
        1. 7.3.7.1 Latch
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Off-Battery Monitoring
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Dissipation and Device Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Creepage Distance
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

TPS37100-Q1 TPS37102-Q1 DYY Package, 14-Pin SOT-23, TPS37100-Q1 (Top View)Figure 5-1 DYY Package,
14-Pin SOT-23, TPS37100-Q1 (Top View)
TPS37100-Q1 TPS37102-Q1 DYY Package,14-Pin SOT-23,TPS37102-Q1 (Top View) PRODUCT PREVIEWFigure 5-2 DYY Package,
14-Pin SOT-23,TPS37102-Q1 (Top View) PRODUCT PREVIEW
Table 5-1 Pin Functions
PINTPS37100-Q1TPS37102-Q1I/ODESCRIPTION
NAMENO.NO.
VDD11IInput Supply Voltage: Supply voltage pin. For noisy systems, bypass with a 0.1µF capacitor to GND.
SENSE33ISense Voltage: Connect this pin to the supply rail that must be monitored. See Section 7.3.2 for more details.Sensing Topology: Overvoltage (OV) or Undervoltage (UV) or Window (OV + UV)
OUT A55OOutput A: OUT A asserts varies on configuration as denoted by in Section 4.See Section 7.3.2 for more details on overvoltage and undervoltage behavior.The active low open-drain output requires an external pullup resistor. See Section 7.3.3 for more details on open-drain output.Output topology: Open-Drain Active-Low
OUT B77OOutput B: OUT B asserts varies on configuration as denoted by in Section 4.See Section 7.3.2 for more details on overvoltage and undervoltage behavior.The active low open-drain output requires an external pullup resistor. See Section 7.3.3 for more details on open-drain output.Output topology: Open-Drain Active-Low
BIST-8OBuilt-In Self-Test: BIST asserts when a logic high input occurs on the BIST_EN pin, this initiates the internal BIST testing. BIST recovers after tBIST to signify BIST completed successfully. BIST remains asserted for a time period longer than tBIST if there is a failure during BIST. BIST active-low open-drain output requires an external pullup resistor. See Section 7.3.7 for more details.
GND99-Ground. GND pin must be electrically connected to the board ground.
AOUT1010OAnalog Out: Output of AOUT is a scaled voltage from the SENSE pin. TPS37100-Q1 can enable or disable Analog Out with AEN Pin. TPS37102-Q1 cannot enable or disable Analog Out and it is in default configuration as denoted in Table 4-1.A 0.1µF is required at AOUT for output stability. See Section 7.3.6 for more details.
AEN11-IAnalog Out Enable: Enables or disables the AOUT pin. A logic high input enables the AOUT. A logic low disables AOUT. AEN pin has an internal 100kΩ pulldown resistor.
BIST_EN-11IBuilt-in Self-test Enable: A rising edge input must occur on the BIST_EN to initate BIST. For variants with latch enabled in the configuration as denoted by in Section 4, BIST_EN enables or disables a latch on OUT A. See Section 7.3.7 for more details.
CTR1212-Release Time Delay: User-programmable release time delay for CTR enabled outputs OUT A and OUT B. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Section 7.3.4 for more details.
CTS1313-Sense Time Delay: User-programmable sense time delay for CTS enabled outputs OUT A and OUT B. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay when CTS is enabled. See Section 7.3.5 for more details.
NC2, 4, 6, 8, 142, 4, 6, 14-NC stands for “No Connect.” The pins are to be left floating.