SNVSCS6A March   2026  – August 2026 TPS7H1301-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Quality Conformance Inspection
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Enable
      2. 9.3.2  Charge Pump
        1. 9.3.2.1 Charge Pump Operation
        2. 9.3.2.2 Foldback Switching
      3. 9.3.3  Startup
      4. 9.3.4  Power Good
      5. 9.3.5  Output Voltage
      6. 9.3.6  Dropout
      7. 9.3.7  Output Voltage Accuracy
      8. 9.3.8  Output Noise
      9. 9.3.9  Power Supply Rejection Ratio
      10. 9.3.10 Stability
        1. 9.3.10.1 Stability of the TPS7H1301
        2. 9.3.10.2 Stability of the TPS7H1302
      11. 9.3.11 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Enable Disable
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application TPS7H1301
      1. 10.2.1 Design Requirements TPS7H1301
      2. 10.2.2 Detailed Design Procedure TPS7H1301
        1. 10.2.2.1 Capacitor Selection
          1. 10.2.2.1.1 Input Capacitor (CIN) Selection
          2. 10.2.2.1.2 CFLY TPS7H1301
          3. 10.2.2.1.3 CPOUT Capacitor TPS7H1301
          4. 10.2.2.1.4 Bypass Capacitors
          5. 10.2.2.1.5 Output Capacitor
        2. 10.2.2.2 Charge Pump Output Resistance
        3. 10.2.2.3 Configuring LDO Output
        4. 10.2.2.4 Output Noise
        5. 10.2.2.5 PSRR Design Implications
        6. 10.2.2.6 Stability Design Considerations
      3. 10.2.3 Application Curves
    3. 10.3 Typical Application TPS7H1301 Parallel Operation
      1. 10.3.1 Design Requirements
      2. 10.3.2 Detailed Design Procedure Parallel TPS7H1301
        1. 10.3.2.1 Parallel Ballast Resistor
      3. 10.3.3 Application Performance Plots
    4. 10.4 Typical Application TPS7H1302
      1. 10.4.1 Design Requirements TPS7H1302
      2. 10.4.2 Detailed Design Procedure TPS7H1302
        1. 10.4.2.1 Capacitor Selection TPS7H1302
        2. 10.4.2.2 CFLY Capacitor TPS7H1302
        3. 10.4.2.3 CPOUT Capacitor TPS7H1302
        4. 10.4.2.4 Stability TPS7H1302
      3. 10.4.3 TPS7H1302 Application Performance Plots
    5. 10.5 TPS7H1302 Low Noise Configuration
      1. 10.5.1 Design Requirements TPS7H1302 Low Noise
      2. 10.5.2 Application Performance Plots
    6. 10.6 Power Supply Recommendations
    7. 10.7 Layout
      1. 10.7.1 Layout Guidelines
      2. 10.7.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 13.1 Tube Information
    3.     88

10.3.2.1 Parallel Ballast Resistor

To calculate the ballast resistor value, calculate the following aspects:

  1. Worst-case output voltage mismatch, ΔVmax
  2. Ballast resistor value (RBallast) and power rating
  3. Voltage drop of the ballast resistor,VDROOP(Ballast)
  4. Configuring feedback resistor network to account for RBallast operation

Worst-Case Output Voltage mismatch ΔVmax

ΔVOUT is determined by the contribution of the LDO output accuracy (VACC) and the precision of the feedback resistors (Rtol). The TPS7H1301 has an output accuracy (VACC) of ±1.5% across voltage, current, temperature and TID; the voltage reference (Vref) has a typical value of 600mV±9mV (min / max).

TI recommends using precision 0.1% feedback resistor; lower tolerance values are permissible; however in parallel applications the lower feedback resistor tolerance directly degrades parallel configuration performance.

Equation 32 is used to calculate the maximum voltage difference possible when considering the combined accuracy of the LDO and feedback resistor tolerances; Equation 33 is a numerical example using 0.1% feedback resistor tolerances.

Equation 32. Δ V m a x = 2 × V A C C % + 2 × R t o l % × V O U T
Equation 33. Δ V m a x = 2 × 1.5 % + 2 × 0.1 % × - 1.8 V = 61 m V

Calculate the Required Ballast Resistance

The ballast resistor requires the designer to select a maximum current difference between the LDOs; the individual typical load is 250mA for this application's 2 LDO 500mA parallel combination, a higher mismatch tolerance of 20% (ΔImax) is sufficient.

For applications in which the individual load current are closer to the Recommended Operating Condition (ROC) maximum current rating of 400mA (per LDO), TI recommends a tighter ΔImax selection (e.g... 10% or lower). Furthermore, the current mismatch needs to be subtracted from the maximum parallel output, which satisfies the individual LDOs IOUT(max) rating of 400mA.

Equation 34. ∆ I m a x =   ∆ V m a x R B 1 + R B 2 = ∆ V m a x 2 × R B ,   R B 1 =   R B 2

Solving for RB in Equation 34 yields Equation 35, which is then applied in Equation 36.

Equation 35. R B = ∆ V m a x 2 × ∆ I m a x
Equation 36. R B = 61 m V 2 × 50 m A = 610 m Ω

Selecting the nearest E192 (0.1% tol) value, RB=612mΩ, for E96 (1% tol) a value of 604mΩ can be selected.

Ballast Resistor Droop Voltage and Power

Equation 37 determines VDROOP(Ballast) is the voltage drop introduced by each RB:

Equation 37. V D R O O P ( B a l l a s t ) =   0.5 × I O U T × R B

Applying Equation 37 is shown in Equation 38:

Equation 38. V D R O O P ( B a l l a s t ) =   0.5 × 500 m A × 612 m Ω = 153 m V

Use Equation 39 to determine the power dissipated in RB; which is shown in Equation 40.

Equation 39. P B a l l a s t =   0.5 × I O U T 2 × R B
Equation 40. P B a l l a s t =   0.5 × 500 m A 2 × 612 m Ω = 38.3 m W

The resultant dissipated power for RB is 38.3mW which can support 1/8W resistors; this is possible due to the precision feedback resistors. Using less precise feedback resistors results in a larger ΔVmax; a substantial increase in ΔVmax increases RB resistance, power dissipation, and VDROOP(Ballast). Selection of feedback resistor (RFB) precision introduces a tradeoff of ΔImax, total output current, and minimum input voltage VIN(min).

Configuring LDO output

The LDO output voltage must now update the feedback network to output a regulated voltage that takes into account VDROOP(Ballast); use Equation 41 to calculate the updated output voltage setting, VOUT(Parallel):

Equation 41. V O U T ( Parallel ) = V O U T - V D R O O P ( B a l l a s t )
Equation 42. V O U T (Parallel) = - 1.8 V - 152.5 m V =   - 1.9525 V

Equation 41 nets a new output voltage setting of –1.9525V; applying Equation 20 is shown in equation Equation 43.

Equation 43. R F B ( B O T ) _ P a r a l l e l = 2000 k Ω - 1.9525 V - 0.6 V - 1 = 887 Ω

Minimum Input Voltage

The minimum input voltage of the TPS7H1301 and TPS7H1302 in parallel operation needs to consider the following:

  1. VDROOP, charge pump voltage drop as configured with CFLY and CCPOUT.
  2. VDROOP(Ballast), voltage drop of RB
  3. VOUT(Parallel), configured output voltage of LDO before RB
  4. VDO, dropout voltage of the LDO at the applied current for each LDO.

Equation 44. V I N ( m i n ) ≥   V D R O O P + V O U T P a r a l l e l + V D O